git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
   4         default 0xa2
   5
   6 config TARGET_SOCFPGA_ARRIA5
   7         bool
   8         select TARGET_SOCFPGA_GEN5
   9
  10 config TARGET_SOCFPGA_ARRIA10
  11         bool
  12         select SPL_BOARD_INIT if SPL
  13         select ALTERA_SDRAM
  14
  15 config TARGET_SOCFPGA_CYCLONE5
  16         bool
  17         select TARGET_SOCFPGA_GEN5
  18
  19 config TARGET_SOCFPGA_GEN5
  20         bool
  21         select ALTERA_SDRAM
  22
  23 choice
  24         prompt "Altera SOCFPGA board select"
  25         optional
  26
  27 config TARGET_SOCFPGA_ARRIA10_SOCDK
  28         bool "Altera SOCFPGA SoCDK (Arria 10)"
  29         select TARGET_SOCFPGA_ARRIA10
  30
  31 config TARGET_SOCFPGA_ARRIA5_SOCDK
  32         bool "Altera SOCFPGA SoCDK (Arria V)"
  33         select TARGET_SOCFPGA_ARRIA5
  34
  35 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  36         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  37         select TARGET_SOCFPGA_CYCLONE5
  38
  39 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  40         bool "Devboards DBM-SoC1 (Cyclone V)"
  41         select TARGET_SOCFPGA_CYCLONE5
  42
  43 config TARGET_SOCFPGA_EBV_SOCRATES
  44         bool "EBV SoCrates (Cyclone V)"
  45         select TARGET_SOCFPGA_CYCLONE5
  46
  47 config TARGET_SOCFPGA_IS1
  48         bool "IS1 (Cyclone V)"
  49         select TARGET_SOCFPGA_CYCLONE5
  50
  51 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  52         bool "samtec VIN|ING FPGA (Cyclone V)"
  53         select BOARD_LATE_INIT
  54         select TARGET_SOCFPGA_CYCLONE5
  55
  56 config TARGET_SOCFPGA_SR1500
  57         bool "SR1500 (Cyclone V)"
  58         select TARGET_SOCFPGA_CYCLONE5
  59
  60 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  61         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  62         select TARGET_SOCFPGA_CYCLONE5
  63
  64 config TARGET_SOCFPGA_TERASIC_DE10_NANO
  65         bool "Terasic DE10-Nano (Cyclone V)"
  66         select TARGET_SOCFPGA_CYCLONE5
  67
  68 config TARGET_SOCFPGA_TERASIC_DE1_SOC
  69         bool "Terasic DE1-SoC (Cyclone V)"
  70         select TARGET_SOCFPGA_CYCLONE5
  71
  72 config TARGET_SOCFPGA_TERASIC_SOCKIT
  73         bool "Terasic SoCkit (Cyclone V)"
  74         select TARGET_SOCFPGA_CYCLONE5
  75
  76 endchoice
  77
  78 config SYS_BOARD
  79         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  80         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  81         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  82         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  83         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  84         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  85         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  86         default "is1" if TARGET_SOCFPGA_IS1
  87         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  88         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  89         default "sr1500" if TARGET_SOCFPGA_SR1500
  90         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  91
  92 config SYS_VENDOR
  93         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  94         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
  95         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  96         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  97         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  98         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  99         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 100         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 101         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 102         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 103
 104 config SYS_SOC
 105         default "socfpga"
 106
 107 config SYS_CONFIG_NAME
 108         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 109         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 110         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 111         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 112         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 113         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 114         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 115         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 116         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 117         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 118         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 119         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 120
 121 endif