git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/reset_manager_gen5.c

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/reset_manager.h>
  12 #include <asm/arch/system_manager.h>
  13
  14 static const struct socfpga_reset_manager *reset_manager_base =
  15                 (void *)SOCFPGA_RSTMGR_ADDRESS;
  16 static const struct socfpga_system_manager *sysmgr_regs =
  17         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  18
  19 /* Assert or de-assert SoCFPGA reset manager reset. */
  20 void socfpga_per_reset(u32 reset, int set)
  21 {
  22         const u32 *reg;
  23         u32 rstmgr_bank = RSTMGR_BANK(reset);
  24
  25         switch (rstmgr_bank) {
  26         case 0:
  27                 reg = &reset_manager_base->mpu_mod_reset;
  28                 break;
  29         case 1:
  30                 reg = &reset_manager_base->per_mod_reset;
  31                 break;
  32         case 2:
  33                 reg = &reset_manager_base->per2_mod_reset;
  34                 break;
  35         case 3:
  36                 reg = &reset_manager_base->brg_mod_reset;
  37                 break;
  38         case 4:
  39                 reg = &reset_manager_base->misc_mod_reset;
  40                 break;
  41
  42         default:
  43                 return;
  44         }
  45
  46         if (set)
  47                 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
  48         else
  49                 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
  50 }
  51
  52 /*
  53  * Assert reset on every peripheral but L4WD0.
  54  * Watchdog must be kept intact to prevent glitches
  55  * and/or hangs.
  56  */
  57 void socfpga_per_reset_all(void)
  58 {
  59         const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  60
  61         writel(~l4wd0, &reset_manager_base->per_mod_reset);
  62         writel(0xffffffff, &reset_manager_base->per2_mod_reset);
  63 }
  64
  65 /*
  66  * Release peripherals from reset based on handoff
  67  */
  68 void reset_deassert_peripherals_handoff(void)
  69 {
  70         writel(0, &reset_manager_base->per_mod_reset);
  71 }
  72
  73 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  74 void socfpga_bridges_reset(int enable)
  75 {
  76         /* For SoCFPGA-VT, this is NOP. */
  77         return;
  78 }
  79 #else
  80
  81 #define L3REGS_REMAP_LWHPS2FPGA_MASK    0x10
  82 #define L3REGS_REMAP_HPS2FPGA_MASK      0x08
  83 #define L3REGS_REMAP_OCRAM_MASK         0x01
  84
  85 void socfpga_bridges_reset(int enable)
  86 {
  87         const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
  88                                 L3REGS_REMAP_HPS2FPGA_MASK |
  89                                 L3REGS_REMAP_OCRAM_MASK;
  90
  91         if (enable) {
  92                 /* brdmodrst */
  93                 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
  94         } else {
  95                 writel(0, &sysmgr_regs->iswgrp_handoff[0]);
  96                 writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
  97
  98                 /* Check signal from FPGA. */
  99                 if (!fpgamgr_test_fpga_ready()) {
 100                         /* FPGA not ready, do nothing. We allow system to boot
 101                          * without FPGA ready. So, return 0 instead of error. */
 102                         printf("%s: FPGA not ready, aborting.\n", __func__);
 103                         return;
 104                 }
 105
 106                 /* brdmodrst */
 107                 writel(0, &reset_manager_base->brg_mod_reset);
 108
 109                 /* Remap the bridges into memory map */
 110                 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
 111         }
 112         return;
 113 }
 114 #endif