git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/arch/nic301.h>
  22 #include <asm/sections.h>
  23 #include <fdtdec.h>
  24 #include <watchdog.h>
  25 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  26 #include <asm/arch/pinmux.h>
  27 #endif
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  32 static struct pl310_regs *const pl310 =
  33         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  34 static struct scu_registers *scu_regs =
  35         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  36 static struct nic301_registers *nic301_regs =
  37         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  38 #endif
  39
  40 static const struct socfpga_system_manager *sysmgr_regs =
  41         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  42
  43 u32 spl_boot_device(void)
  44 {
  45         const u32 bsel = readl(&sysmgr_regs->bootinfo);
  46
  47         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  48         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  49                 return BOOT_DEVICE_RAM;
  50         case 0x2:       /* NAND Flash (1.8V) */
  51         case 0x3:       /* NAND Flash (3.0V) */
  52                 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  53                 return BOOT_DEVICE_NAND;
  54         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  55         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  56                 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  57                 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  58                 return BOOT_DEVICE_MMC1;
  59         case 0x6:       /* QSPI Flash (1.8V) */
  60         case 0x7:       /* QSPI Flash (3.0V) */
  61                 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  62                 return BOOT_DEVICE_SPI;
  63         default:
  64                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  65                 hang();
  66         }
  67 }
  68
  69 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  70 static void socfpga_nic301_slave_ns(void)
  71 {
  72         writel(0x1, &nic301_regs->lwhps2fpgaregs);
  73         writel(0x1, &nic301_regs->hps2fpgaregs);
  74         writel(0x1, &nic301_regs->acp);
  75         writel(0x1, &nic301_regs->rom);
  76         writel(0x1, &nic301_regs->ocram);
  77         writel(0x1, &nic301_regs->sdrdata);
  78 }
  79
  80 void board_init_f(ulong dummy)
  81 {
  82 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  83         const struct cm_config *cm_default_cfg = cm_get_default_config();
  84 #endif
  85         unsigned long sdram_size;
  86         unsigned long reg;
  87
  88         /*
  89          * First C code to run. Clear fake OCRAM ECC first as SBE
  90          * and DBE might triggered during power on
  91          */
  92         reg = readl(&sysmgr_regs->eccgrp_ocram);
  93         if (reg & SYSMGR_ECC_OCRAM_SERR)
  94                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  95                        &sysmgr_regs->eccgrp_ocram);
  96         if (reg & SYSMGR_ECC_OCRAM_DERR)
  97                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  98                        &sysmgr_regs->eccgrp_ocram);
  99
 100         memset(__bss_start, 0, __bss_end - __bss_start);
 101
 102         socfpga_nic301_slave_ns();
 103
 104         /* Configure ARM MPU SNSAC register. */
 105         setbits_le32(&scu_regs->sacr, 0xfff);
 106
 107         /* Remap SDRAM to 0x0 */
 108         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 109         writel(0x1, &pl310->pl310_addr_filter_start);
 110
 111 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
 112         debug("Freezing all I/O banks\n");
 113         /* freeze all IO banks */
 114         sys_mgr_frzctrl_freeze_req();
 115
 116         /* Put everything into reset but L4WD0. */
 117         socfpga_per_reset_all();
 118         /* Put FPGA bridges into reset too. */
 119         socfpga_bridges_reset(1);
 120
 121         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 122         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 123         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 124
 125         timer_init();
 126
 127         debug("Reconfigure Clock Manager\n");
 128         /* reconfigure the PLLs */
 129         if (cm_basic_init(cm_default_cfg))
 130                 hang();
 131
 132         /* Enable bootrom to configure IOs. */
 133         sysmgr_config_warmrstcfgio(1);
 134
 135         /* configure the IOCSR / IO buffer settings */
 136         if (scan_mgr_configure_iocsr())
 137                 hang();
 138
 139         sysmgr_config_warmrstcfgio(0);
 140
 141         /* configure the pin muxing through system manager */
 142         sysmgr_config_warmrstcfgio(1);
 143         sysmgr_pinmux_init();
 144         sysmgr_config_warmrstcfgio(0);
 145
 146 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 147
 148         /* De-assert reset for peripherals and bridges based on handoff */
 149         reset_deassert_peripherals_handoff();
 150         socfpga_bridges_reset(0);
 151
 152         debug("Unfreezing/Thaw all I/O banks\n");
 153         /* unfreeze / thaw all IO banks */
 154         sys_mgr_frzctrl_thaw_req();
 155
 156         /* enable console uart printing */
 157         preloader_console_init();
 158
 159         if (sdram_mmr_init_full(0xffffffff) != 0) {
 160                 puts("SDRAM init failed.\n");
 161                 hang();
 162         }
 163
 164         debug("SDRAM: Calibrating PHY\n");
 165         /* SDRAM calibration */
 166         if (sdram_calibration_full() == 0) {
 167                 puts("SDRAM calibration failed.\n");
 168                 hang();
 169         }
 170
 171         sdram_size = sdram_calculate_size();
 172         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 173
 174         /* Sanity check ensure correct SDRAM size specified */
 175         if (get_ram_size(0, sdram_size) != sdram_size) {
 176                 puts("SDRAM size check failed!\n");
 177                 hang();
 178         }
 179
 180         socfpga_bridges_reset(1);
 181
 182         /* Configure simple malloc base pointer into RAM. */
 183         gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 184 }
 185 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 186 void spl_board_init(void)
 187 {
 188         /* configuring the clock based on handoff */
 189         cm_basic_init(gd->fdt_blob);
 190         WATCHDOG_RESET();
 191
 192         config_dedicated_pins(gd->fdt_blob);
 193         WATCHDOG_RESET();
 194
 195         /* Release UART from reset */
 196         socfpga_reset_uart(0);
 197
 198         /* enable console uart printing */
 199         preloader_console_init();
 200 }
 201
 202 void board_init_f(ulong dummy)
 203 {
 204         /*
 205          * Configure Clock Manager to use intosc clock instead external osc to
 206          * ensure success watchdog operation. We do it as early as possible.
 207          */
 208         cm_use_intosc();
 209
 210         socfpga_watchdog_disable();
 211
 212         arch_early_init_r();
 213
 214 #ifdef CONFIG_HW_WATCHDOG
 215         /* release osc1 watchdog timer 0 from reset */
 216         socfpga_reset_deassert_osc1wd0();
 217
 218         /* reconfigure and enable the watchdog */
 219         hw_watchdog_init();
 220         WATCHDOG_RESET();
 221 #endif /* CONFIG_HW_WATCHDOG */
 222 }
 223 #endif