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[u-boot] / arch / arm / mach-tegra / tegra124 / xusb-padctl.c
1 /*
2  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * SPDX-License-Identifier: GPL-2.0
5  */
6
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
8
9 #include <common.h>
10 #include <errno.h>
11 #include <dm/of_access.h>
12 #include <dm/ofnode.h>
13
14 #include "../xusb-padctl-common.h"
15
16 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
17
18 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
19 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
20 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
21 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
22
23 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
24 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
25 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
26 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
27
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
32
33 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
34 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
35 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
36 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
39
40 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
41 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
42 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
43
44 enum tegra124_function {
45         TEGRA124_FUNC_SNPS,
46         TEGRA124_FUNC_XUSB,
47         TEGRA124_FUNC_UART,
48         TEGRA124_FUNC_PCIE,
49         TEGRA124_FUNC_USB3,
50         TEGRA124_FUNC_SATA,
51         TEGRA124_FUNC_RSVD,
52 };
53
54 static const char *const tegra124_functions[] = {
55         "snps",
56         "xusb",
57         "uart",
58         "pcie",
59         "usb3",
60         "sata",
61         "rsvd",
62 };
63
64 static const unsigned int tegra124_otg_functions[] = {
65         TEGRA124_FUNC_SNPS,
66         TEGRA124_FUNC_XUSB,
67         TEGRA124_FUNC_UART,
68         TEGRA124_FUNC_RSVD,
69 };
70
71 static const unsigned int tegra124_usb_functions[] = {
72         TEGRA124_FUNC_SNPS,
73         TEGRA124_FUNC_XUSB,
74 };
75
76 static const unsigned int tegra124_pci_functions[] = {
77         TEGRA124_FUNC_PCIE,
78         TEGRA124_FUNC_USB3,
79         TEGRA124_FUNC_SATA,
80         TEGRA124_FUNC_RSVD,
81 };
82
83 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)     \
84         {                                                               \
85                 .name = _name,                                          \
86                 .offset = _offset,                                      \
87                 .shift = _shift,                                        \
88                 .mask = _mask,                                          \
89                 .iddq = _iddq,                                          \
90                 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
91                 .funcs = tegra124_##_funcs##_functions,                 \
92         }
93
94 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
95         TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
96         TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
97         TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
98         TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
99         TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
100         TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
101         TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
102         TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
103         TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
104         TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
105         TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
106         TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
107 };
108
109 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
110 {
111         u32 value;
112
113         if (padctl->enable++ > 0)
114                 return 0;
115
116         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
117         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
118         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
119
120         udelay(100);
121
122         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
123         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
124         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
125
126         udelay(100);
127
128         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
129         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
130         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
131
132         return 0;
133 }
134
135 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
136 {
137         u32 value;
138
139         if (padctl->enable == 0) {
140                 error("unbalanced enable/disable");
141                 return 0;
142         }
143
144         if (--padctl->enable > 0)
145                 return 0;
146
147         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
148         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
149         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
150
151         udelay(100);
152
153         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
154         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
155         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
156
157         udelay(100);
158
159         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
160         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
161         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
162
163         return 0;
164 }
165
166 static int phy_prepare(struct tegra_xusb_phy *phy)
167 {
168         return tegra_xusb_padctl_enable(phy->padctl);
169 }
170
171 static int phy_unprepare(struct tegra_xusb_phy *phy)
172 {
173         return tegra_xusb_padctl_disable(phy->padctl);
174 }
175
176 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
177 {
178         struct tegra_xusb_padctl *padctl = phy->padctl;
179         int err = -ETIMEDOUT;
180         unsigned long start;
181         u32 value;
182
183         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
184         value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
185         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
186
187         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
188         value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
189                  XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
190                  XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
191         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
192
193         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
194         value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
195         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
196
197         start = get_timer(0);
198
199         while (get_timer(start) < 50) {
200                 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
201                 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
202                         err = 0;
203                         break;
204                 }
205         }
206
207         return err;
208 }
209
210 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
211 {
212         struct tegra_xusb_padctl *padctl = phy->padctl;
213         u32 value;
214
215         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
216         value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
217         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
218
219         return 0;
220 }
221
222 static int sata_phy_enable(struct tegra_xusb_phy *phy)
223 {
224         struct tegra_xusb_padctl *padctl = phy->padctl;
225         int err = -ETIMEDOUT;
226         unsigned long start;
227         u32 value;
228
229         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
230         value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
231         value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
232         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
233
234         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
235         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
236         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
237         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
238
239         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
240         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
241         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
242
243         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
244         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
245         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
246
247         start = get_timer(0);
248
249         while (get_timer(start) < 50) {
250                 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
251                 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
252                         err = 0;
253                         break;
254                 }
255         }
256
257         return err;
258 }
259
260 static int sata_phy_disable(struct tegra_xusb_phy *phy)
261 {
262         struct tegra_xusb_padctl *padctl = phy->padctl;
263         u32 value;
264
265         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
266         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
267         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
268
269         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
270         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
271         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
272
273         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
274         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
275         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
276         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
277
278         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
279         value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
280         value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
281         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
282
283         return 0;
284 }
285
286 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
287         .prepare = phy_prepare,
288         .enable = pcie_phy_enable,
289         .disable = pcie_phy_disable,
290         .unprepare = phy_unprepare,
291 };
292
293 static const struct tegra_xusb_phy_ops sata_phy_ops = {
294         .prepare = phy_prepare,
295         .enable = sata_phy_enable,
296         .disable = sata_phy_disable,
297         .unprepare = phy_unprepare,
298 };
299
300 static struct tegra_xusb_phy tegra124_phys[] = {
301         {
302                 .type = TEGRA_XUSB_PADCTL_PCIE,
303                 .ops = &pcie_phy_ops,
304                 .padctl = &padctl,
305         },
306         {
307                 .type = TEGRA_XUSB_PADCTL_SATA,
308                 .ops = &sata_phy_ops,
309                 .padctl = &padctl,
310         },
311 };
312
313 static const struct tegra_xusb_padctl_soc tegra124_socdata = {
314         .lanes = tegra124_lanes,
315         .num_lanes = ARRAY_SIZE(tegra124_lanes),
316         .functions = tegra124_functions,
317         .num_functions = ARRAY_SIZE(tegra124_functions),
318         .phys = tegra124_phys,
319         .num_phys = ARRAY_SIZE(tegra124_phys),
320 };
321
322 void tegra_xusb_padctl_init(void)
323 {
324         ofnode nodes[1];
325         int count = 0;
326         int ret;
327
328         debug("%s: start\n", __func__);
329         if (of_live_active()) {
330                 struct device_node *np = of_find_compatible_node(NULL, NULL,
331                                                 "nvidia,tegra124-xusb-padctl");
332
333                 debug("np=%p\n", np);
334                 if (np) {
335                         nodes[0] = np_to_ofnode(np);
336                         count = 1;
337                 }
338         } else {
339                 int node_offsets[1];
340                 int i;
341
342                 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
343                                 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
344                                 node_offsets, ARRAY_SIZE(node_offsets));
345                 for (i = 0; i < count; i++)
346                         nodes[i] = offset_to_ofnode(node_offsets[i]);
347         }
348
349         ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
350         debug("%s: done, ret=%d\n", __func__, ret);
351 }