git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/clk/pll-ld4.c

   1 /*
   2  * Copyright (C) 2013-2014 Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/io.h>
  10
  11 #include "../init.h"
  12 #include "../sc-regs.h"
  13 #include "../sg-regs.h"
  14 #include "pll.h"
  15
  16 static void upll_init(void)
  17 {
  18         u32 tmp, clk_mode_upll, clk_mode_axosel;
  19
  20         tmp = readl(SG_PINMON0);
  21         clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
  22         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
  23
  24         /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
  25         tmp = readl(SC_UPLLCTRL);
  26         tmp &= ~0x18000000;
  27         writel(tmp, SC_UPLLCTRL);
  28
  29         if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
  30                 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
  31                     clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
  32                         /* AXO: 25MHz */
  33                         tmp &= ~0x07ffffff;
  34                         tmp |= 0x0228f5c0;
  35                 } else {
  36                         /* AXO: default 24.576MHz */
  37                         tmp &= ~0x07ffffff;
  38                         tmp |= 0x02328000;
  39                 }
  40         }
  41
  42         writel(tmp, SC_UPLLCTRL);
  43
  44         /* set 1 to K_LD(UPLLCTRL.bit[27]) */
  45         tmp |= 0x08000000;
  46         writel(tmp, SC_UPLLCTRL);
  47
  48         /* wait 10 usec */
  49         udelay(10);
  50
  51         /* set 1 to SNRT(UPLLCTRL.bit[28]) */
  52         tmp |= 0x10000000;
  53         writel(tmp, SC_UPLLCTRL);
  54 }
  55
  56 static void vpll_init(void)
  57 {
  58         u32 tmp, clk_mode_axosel;
  59
  60         tmp = readl(SG_PINMON0);
  61         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
  62
  63         /* set 1 to VPLA27WP and VPLA27WP */
  64         tmp = readl(SC_VPLL27ACTRL);
  65         tmp |= 0x00000001;
  66         writel(tmp, SC_VPLL27ACTRL);
  67         tmp = readl(SC_VPLL27BCTRL);
  68         tmp |= 0x00000001;
  69         writel(tmp, SC_VPLL27BCTRL);
  70
  71         /* Set 0 to VPLA_K_LD and VPLB_K_LD */
  72         tmp = readl(SC_VPLL27ACTRL3);
  73         tmp &= ~0x10000000;
  74         writel(tmp, SC_VPLL27ACTRL3);
  75         tmp = readl(SC_VPLL27BCTRL3);
  76         tmp &= ~0x10000000;
  77         writel(tmp, SC_VPLL27BCTRL3);
  78
  79         /* Set 0 to VPLA_SNRST and VPLB_SNRST */
  80         tmp = readl(SC_VPLL27ACTRL2);
  81         tmp &= ~0x10000000;
  82         writel(tmp, SC_VPLL27ACTRL2);
  83         tmp = readl(SC_VPLL27BCTRL2);
  84         tmp &= ~0x10000000;
  85         writel(tmp, SC_VPLL27BCTRL2);
  86
  87         /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
  88         tmp = readl(SC_VPLL27ACTRL2);
  89         tmp &= ~0x0000007f;
  90         tmp |= 0x00000020;
  91         writel(tmp, SC_VPLL27ACTRL2);
  92         tmp = readl(SC_VPLL27BCTRL2);
  93         tmp &= ~0x0000007f;
  94         tmp |= 0x00000020;
  95         writel(tmp, SC_VPLL27BCTRL2);
  96
  97         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
  98             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
  99                 /* AXO: 25MHz */
 100                 tmp = readl(SC_VPLL27ACTRL3);
 101                 tmp &= ~0x000fffff;
 102                 tmp |= 0x00066664;
 103                 writel(tmp, SC_VPLL27ACTRL3);
 104                 tmp = readl(SC_VPLL27BCTRL3);
 105                 tmp &= ~0x000fffff;
 106                 tmp |= 0x00066664;
 107                 writel(tmp, SC_VPLL27BCTRL3);
 108         } else {
 109                 /* AXO: default 24.576MHz */
 110                 tmp = readl(SC_VPLL27ACTRL3);
 111                 tmp &= ~0x000fffff;
 112                 tmp |= 0x000f5800;
 113                 writel(tmp, SC_VPLL27ACTRL3);
 114                 tmp = readl(SC_VPLL27BCTRL3);
 115                 tmp &= ~0x000fffff;
 116                 tmp |= 0x000f5800;
 117                 writel(tmp, SC_VPLL27BCTRL3);
 118         }
 119
 120         /* Set 1 to VPLA_K_LD and VPLB_K_LD */
 121         tmp = readl(SC_VPLL27ACTRL3);
 122         tmp |= 0x10000000;
 123         writel(tmp, SC_VPLL27ACTRL3);
 124         tmp = readl(SC_VPLL27BCTRL3);
 125         tmp |= 0x10000000;
 126         writel(tmp, SC_VPLL27BCTRL3);
 127
 128         /* wait 10 usec */
 129         udelay(10);
 130
 131         /* Set 0 to VPLA_SNRST and VPLB_SNRST */
 132         tmp = readl(SC_VPLL27ACTRL2);
 133         tmp |= 0x10000000;
 134         writel(tmp, SC_VPLL27ACTRL2);
 135         tmp = readl(SC_VPLL27BCTRL2);
 136         tmp |= 0x10000000;
 137         writel(tmp, SC_VPLL27BCTRL2);
 138
 139         /* set 0 to VPLA27WP and VPLA27WP */
 140         tmp = readl(SC_VPLL27ACTRL);
 141         tmp &= ~0x00000001;
 142         writel(tmp, SC_VPLL27ACTRL);
 143         tmp = readl(SC_VPLL27BCTRL);
 144         tmp |= ~0x00000001;
 145         writel(tmp, SC_VPLL27BCTRL);
 146 }
 147
 148 void uniphier_ld4_pll_init(void)
 149 {
 150         upll_init();
 151         vpll_init();
 152         uniphier_ld4_dpll_ssc_en();
 153 }