git.sur5r.net Git - u-boot/blob - arch/x86/dts/bayleybay.dts

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
  10 #include <dt-bindings/gpio/x86-gpio.h>
  11 #include <dt-bindings/interrupt-router/intel-irq.h>
  12
  13 /include/ "skeleton.dtsi"
  14 /include/ "keyboard.dtsi"
  15 /include/ "serial.dtsi"
  16 /include/ "rtc.dtsi"
  17 /include/ "tsc_timer.dtsi"
  18 /include/ "coreboot_fb.dtsi"
  19
  20 / {
  21         model = "Intel Bayley Bay";
  22         compatible = "intel,bayleybay", "intel,baytrail";
  23
  24         aliases {
  25                 serial0 = &serial;
  26                 spi0 = &spi;
  27         };
  28
  29         config {
  30                 silent_console = <0>;
  31         };
  32
  33         chosen {
  34                 stdout-path = "/serial";
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "intel,baytrail-cpu";
  44                         reg = <0>;
  45                         intel,apic-id = <0>;
  46                 };
  47
  48                 cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "intel,baytrail-cpu";
  51                         reg = <1>;
  52                         intel,apic-id = <2>;
  53                 };
  54
  55                 cpu@2 {
  56                         device_type = "cpu";
  57                         compatible = "intel,baytrail-cpu";
  58                         reg = <2>;
  59                         intel,apic-id = <4>;
  60                 };
  61
  62                 cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "intel,baytrail-cpu";
  65                         reg = <3>;
  66                         intel,apic-id = <6>;
  67                 };
  68         };
  69
  70         pch_pinctrl {
  71                 compatible = "intel,x86-pinctrl";
  72                 reg = <0 0>;
  73
  74                 /*
  75                  * As of today, the latest version FSP (gold4) for BayTrail
  76                  * misses the PAD configuration of the SD controller's Card
  77                  * Detect signal. The default PAD value for the CD pin sets
  78                  * the pin to work in GPIO mode, which causes card detect
  79                  * status cannot be reflected by the Present State register
  80                  * in the SD controller (bit 16 & bit 18 are always zero).
  81                  *
  82                  * Configure this pin to function 1 (SD controller).
  83                  */
  84                 sdmmc3_cd@0 {
  85                         pad-offset = <0x3a0>;
  86                         mode-func = <1>;
  87                 };
  88         };
  89
  90         pci {
  91                 compatible = "pci-x86";
  92                 #address-cells = <3>;
  93                 #size-cells = <2>;
  94                 u-boot,dm-pre-reloc;
  95                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  96                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  97                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  98
  99                 pch@1f,0 {
 100                         reg = <0x0000f800 0 0 0 0>;
 101                         compatible = "intel,pch9";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104
 105                         irq-router {
 106                                 compatible = "intel,irq-router";
 107                                 intel,pirq-config = "ibase";
 108                                 intel,ibase-offset = <0x50>;
 109                                 intel,actl-addr = <0>;
 110                                 intel,pirq-link = <8 8>;
 111                                 intel,pirq-mask = <0xdee0>;
 112                                 intel,pirq-routing = <
 113                                         /* BayTrail PCI devices */
 114                                         PCI_BDF(0, 2, 0) INTA PIRQA
 115                                         PCI_BDF(0, 3, 0) INTA PIRQA
 116                                         PCI_BDF(0, 16, 0) INTA PIRQA
 117                                         PCI_BDF(0, 17, 0) INTA PIRQA
 118                                         PCI_BDF(0, 18, 0) INTA PIRQA
 119                                         PCI_BDF(0, 19, 0) INTA PIRQA
 120                                         PCI_BDF(0, 20, 0) INTA PIRQA
 121                                         PCI_BDF(0, 21, 0) INTA PIRQA
 122                                         PCI_BDF(0, 22, 0) INTA PIRQA
 123                                         PCI_BDF(0, 23, 0) INTA PIRQA
 124                                         PCI_BDF(0, 24, 0) INTA PIRQA
 125                                         PCI_BDF(0, 24, 1) INTC PIRQC
 126                                         PCI_BDF(0, 24, 2) INTD PIRQD
 127                                         PCI_BDF(0, 24, 3) INTB PIRQB
 128                                         PCI_BDF(0, 24, 4) INTA PIRQA
 129                                         PCI_BDF(0, 24, 5) INTC PIRQC
 130                                         PCI_BDF(0, 24, 6) INTD PIRQD
 131                                         PCI_BDF(0, 24, 7) INTB PIRQB
 132                                         PCI_BDF(0, 26, 0) INTA PIRQA
 133                                         PCI_BDF(0, 27, 0) INTA PIRQA
 134                                         PCI_BDF(0, 28, 0) INTA PIRQA
 135                                         PCI_BDF(0, 28, 1) INTB PIRQB
 136                                         PCI_BDF(0, 28, 2) INTC PIRQC
 137                                         PCI_BDF(0, 28, 3) INTD PIRQD
 138                                         PCI_BDF(0, 29, 0) INTA PIRQA
 139                                         PCI_BDF(0, 30, 0) INTA PIRQA
 140                                         PCI_BDF(0, 30, 1) INTD PIRQD
 141                                         PCI_BDF(0, 30, 2) INTB PIRQB
 142                                         PCI_BDF(0, 30, 3) INTC PIRQC
 143                                         PCI_BDF(0, 30, 4) INTD PIRQD
 144                                         PCI_BDF(0, 30, 5) INTB PIRQB
 145                                         PCI_BDF(0, 31, 3) INTB PIRQB
 146
 147                                         /*
 148                                          * PCIe root ports downstream
 149                                          * interrupts
 150                                          */
 151                                         PCI_BDF(1, 0, 0) INTA PIRQA
 152                                         PCI_BDF(1, 0, 0) INTB PIRQB
 153                                         PCI_BDF(1, 0, 0) INTC PIRQC
 154                                         PCI_BDF(1, 0, 0) INTD PIRQD
 155                                         PCI_BDF(2, 0, 0) INTA PIRQB
 156                                         PCI_BDF(2, 0, 0) INTB PIRQC
 157                                         PCI_BDF(2, 0, 0) INTC PIRQD
 158                                         PCI_BDF(2, 0, 0) INTD PIRQA
 159                                         PCI_BDF(3, 0, 0) INTA PIRQC
 160                                         PCI_BDF(3, 0, 0) INTB PIRQD
 161                                         PCI_BDF(3, 0, 0) INTC PIRQA
 162                                         PCI_BDF(3, 0, 0) INTD PIRQB
 163                                         PCI_BDF(4, 0, 0) INTA PIRQD
 164                                         PCI_BDF(4, 0, 0) INTB PIRQA
 165                                         PCI_BDF(4, 0, 0) INTC PIRQB
 166                                         PCI_BDF(4, 0, 0) INTD PIRQC
 167                                 >;
 168                         };
 169
 170                         spi: spi {
 171                                 #address-cells = <1>;
 172                                 #size-cells = <0>;
 173                                 compatible = "intel,ich9-spi";
 174                                 spi-flash@0 {
 175                                         #address-cells = <1>;
 176                                         #size-cells = <1>;
 177                                         reg = <0>;
 178                                         compatible = "winbond,w25q64dw",
 179                                                 "spi-flash";
 180                                         memory-map = <0xff800000 0x00800000>;
 181                                         rw-mrc-cache {
 182                                                 label = "rw-mrc-cache";
 183                                                 reg = <0x006e0000 0x00010000>;
 184                                         };
 185                                 };
 186                         };
 187
 188                         gpioa {
 189                                 compatible = "intel,ich6-gpio";
 190                                 u-boot,dm-pre-reloc;
 191                                 reg = <0 0x20>;
 192                                 bank-name = "A";
 193                                 use-lvl-write-cache;
 194                         };
 195
 196                         gpiob {
 197                                 compatible = "intel,ich6-gpio";
 198                                 u-boot,dm-pre-reloc;
 199                                 reg = <0x20 0x20>;
 200                                 bank-name = "B";
 201                                 use-lvl-write-cache;
 202                         };
 203
 204                         gpioc {
 205                                 compatible = "intel,ich6-gpio";
 206                                 u-boot,dm-pre-reloc;
 207                                 reg = <0x40 0x20>;
 208                                 bank-name = "C";
 209                                 use-lvl-write-cache;
 210                         };
 211
 212                         gpiod {
 213                                 compatible = "intel,ich6-gpio";
 214                                 u-boot,dm-pre-reloc;
 215                                 reg = <0x60 0x20>;
 216                                 bank-name = "D";
 217                                 use-lvl-write-cache;
 218                         };
 219
 220                         gpioe {
 221                                 compatible = "intel,ich6-gpio";
 222                                 u-boot,dm-pre-reloc;
 223                                 reg = <0x80 0x20>;
 224                                 bank-name = "E";
 225                                 use-lvl-write-cache;
 226                         };
 227
 228                         gpiof {
 229                                 compatible = "intel,ich6-gpio";
 230                                 u-boot,dm-pre-reloc;
 231                                 reg = <0xA0 0x20>;
 232                                 bank-name = "F";
 233                                 use-lvl-write-cache;
 234                         };
 235                 };
 236         };
 237
 238         fsp {
 239                 compatible = "intel,baytrail-fsp";
 240                 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
 241                 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
 242                 fsp,mrc-init-spd-addr1 = <0xa0>;
 243                 fsp,mrc-init-spd-addr2 = <0xa2>;
 244                 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
 245                 fsp,enable-sdio;
 246                 fsp,enable-sdcard;
 247                 fsp,enable-hsuart1;
 248                 fsp,enable-spi;
 249                 fsp,enable-sata;
 250                 fsp,sata-mode = <SATA_MODE_AHCI>;
 251                 fsp,lpe-mode = <LPE_MODE_PCI>;
 252                 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 253                 fsp,enable-dma0;
 254                 fsp,enable-dma1;
 255                 fsp,enable-i2c0;
 256                 fsp,enable-i2c1;
 257                 fsp,enable-i2c2;
 258                 fsp,enable-i2c3;
 259                 fsp,enable-i2c4;
 260                 fsp,enable-i2c5;
 261                 fsp,enable-i2c6;
 262                 fsp,enable-pwm0;
 263                 fsp,enable-pwm1;
 264                 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 265                 fsp,aperture-size = <APERTURE_SIZE_256MB>;
 266                 fsp,gtt-size = <GTT_SIZE_2MB>;
 267                 fsp,scc-mode = <SCC_MODE_PCI>;
 268                 fsp,os-selection = <OS_SELECTION_LINUX>;
 269                 fsp,emmc45-ddr50-enabled;
 270                 fsp,emmc45-retune-timer-value = <8>;
 271                 fsp,enable-igd;
 272         };
 273
 274         microcode {
 275                 update@0 {
 276 #include "microcode/m0230671117.dtsi"
 277                 };
 278                 update@1 {
 279 #include "microcode/m0130673325.dtsi"
 280                 };
 281                 update@2 {
 282 #include "microcode/m0130679907.dtsi"
 283                 };
 284         };
 285
 286 };