git.sur5r.net Git - u-boot/blob - arch/x86/dts/conga-qeval20-qa3-e3845.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /dts-v1/;
   9
  10 #include <asm/arch-baytrail/fsp/fsp_configs.h>
  11 #include <dt-bindings/gpio/x86-gpio.h>
  12 #include <dt-bindings/interrupt-router/intel-irq.h>
  13
  14 /include/ "skeleton.dtsi"
  15 /include/ "serial.dtsi"
  16 /include/ "rtc.dtsi"
  17 /include/ "tsc_timer.dtsi"
  18
  19 / {
  20         model = "congatec-QEVAL20-QA3-E3845";
  21         compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
  22
  23         aliases {
  24                 serial0 = &serial;
  25                 spi0 = &spi;
  26         };
  27
  28         config {
  29                 silent_console = <0>;
  30         };
  31
  32         pch_pinctrl {
  33                 compatible = "intel,x86-pinctrl";
  34                 reg = <0 0>;
  35
  36                 /*
  37                  * As of today, the latest version FSP (gold4) for BayTrail
  38                  * misses the PAD configuration of the SD controller's Card
  39                  * Detect signal. The default PAD value for the CD pin sets
  40                  * the pin to work in GPIO mode, which causes card detect
  41                  * status cannot be reflected by the Present State register
  42                  * in the SD controller (bit 16 & bit 18 are always zero).
  43                  *
  44                  * Configure this pin to function 1 (SD controller).
  45                  */
  46                 sdmmc3_cd@0 {
  47                         pad-offset = <0x3a0>;
  48                         mode-func = <1>;
  49                 };
  50
  51                 /* Add SMBus PAD configuration */
  52                 smbus_clk@0 {
  53                         pad-offset = <0x580>;
  54                         mode-func = <1>;
  55                 };
  56
  57                 smbus_data@0 {
  58                         pad-offset = <0x5a0>;
  59                         mode-func = <1>;
  60                 };
  61         };
  62
  63         chosen {
  64                 stdout-path = "/serial";
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "intel,baytrail-cpu";
  74                         reg = <0>;
  75                         intel,apic-id = <0>;
  76                 };
  77
  78                 cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "intel,baytrail-cpu";
  81                         reg = <1>;
  82                         intel,apic-id = <2>;
  83                 };
  84
  85                 cpu@2 {
  86                         device_type = "cpu";
  87                         compatible = "intel,baytrail-cpu";
  88                         reg = <2>;
  89                         intel,apic-id = <4>;
  90                 };
  91
  92                 cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "intel,baytrail-cpu";
  95                         reg = <3>;
  96                         intel,apic-id = <6>;
  97                 };
  98         };
  99
 100         pci {
 101                 compatible = "intel,pci-baytrail", "pci-x86";
 102                 #address-cells = <3>;
 103                 #size-cells = <2>;
 104                 u-boot,dm-pre-reloc;
 105                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 106                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 107                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 108
 109                 pch@1f,0 {
 110                         reg = <0x0000f800 0 0 0 0>;
 111                         compatible = "pci8086,0f1c", "intel,pch9";
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114
 115                         irq-router {
 116                                 compatible = "intel,irq-router";
 117                                 intel,pirq-config = "ibase";
 118                                 intel,ibase-offset = <0x50>;
 119                                 intel,actl-addr = <0>;
 120                                 intel,pirq-link = <8 8>;
 121                                 intel,pirq-mask = <0xdee0>;
 122                                 intel,pirq-routing = <
 123                                         /* BayTrail PCI devices */
 124                                         PCI_BDF(0, 2, 0) INTA PIRQA
 125                                         PCI_BDF(0, 3, 0) INTA PIRQA
 126                                         PCI_BDF(0, 16, 0) INTA PIRQA
 127                                         PCI_BDF(0, 17, 0) INTA PIRQA
 128                                         PCI_BDF(0, 18, 0) INTA PIRQA
 129                                         PCI_BDF(0, 19, 0) INTA PIRQA
 130                                         PCI_BDF(0, 20, 0) INTA PIRQA
 131                                         PCI_BDF(0, 21, 0) INTA PIRQA
 132                                         PCI_BDF(0, 22, 0) INTA PIRQA
 133                                         PCI_BDF(0, 23, 0) INTA PIRQA
 134                                         PCI_BDF(0, 24, 0) INTA PIRQA
 135                                         PCI_BDF(0, 24, 1) INTC PIRQC
 136                                         PCI_BDF(0, 24, 2) INTD PIRQD
 137                                         PCI_BDF(0, 24, 3) INTB PIRQB
 138                                         PCI_BDF(0, 24, 4) INTA PIRQA
 139                                         PCI_BDF(0, 24, 5) INTC PIRQC
 140                                         PCI_BDF(0, 24, 6) INTD PIRQD
 141                                         PCI_BDF(0, 24, 7) INTB PIRQB
 142                                         PCI_BDF(0, 26, 0) INTA PIRQA
 143                                         PCI_BDF(0, 27, 0) INTA PIRQA
 144                                         PCI_BDF(0, 28, 0) INTA PIRQA
 145                                         PCI_BDF(0, 28, 1) INTB PIRQB
 146                                         PCI_BDF(0, 28, 2) INTC PIRQC
 147                                         PCI_BDF(0, 28, 3) INTD PIRQD
 148                                         PCI_BDF(0, 29, 0) INTA PIRQA
 149                                         PCI_BDF(0, 30, 0) INTA PIRQA
 150                                         PCI_BDF(0, 30, 1) INTD PIRQD
 151                                         PCI_BDF(0, 30, 2) INTB PIRQB
 152                                         PCI_BDF(0, 30, 3) INTC PIRQC
 153                                         PCI_BDF(0, 30, 4) INTD PIRQD
 154                                         PCI_BDF(0, 30, 5) INTB PIRQB
 155                                         PCI_BDF(0, 31, 3) INTB PIRQB
 156
 157                                         /*
 158                                          * PCIe root ports downstream
 159                                          * interrupts
 160                                          */
 161                                         PCI_BDF(1, 0, 0) INTA PIRQA
 162                                         PCI_BDF(1, 0, 0) INTB PIRQB
 163                                         PCI_BDF(1, 0, 0) INTC PIRQC
 164                                         PCI_BDF(1, 0, 0) INTD PIRQD
 165                                         PCI_BDF(2, 0, 0) INTA PIRQB
 166                                         PCI_BDF(2, 0, 0) INTB PIRQC
 167                                         PCI_BDF(2, 0, 0) INTC PIRQD
 168                                         PCI_BDF(2, 0, 0) INTD PIRQA
 169                                         PCI_BDF(3, 0, 0) INTA PIRQC
 170                                         PCI_BDF(3, 0, 0) INTB PIRQD
 171                                         PCI_BDF(3, 0, 0) INTC PIRQA
 172                                         PCI_BDF(3, 0, 0) INTD PIRQB
 173                                         PCI_BDF(4, 0, 0) INTA PIRQD
 174                                         PCI_BDF(4, 0, 0) INTB PIRQA
 175                                         PCI_BDF(4, 0, 0) INTC PIRQB
 176                                         PCI_BDF(4, 0, 0) INTD PIRQC
 177                                 >;
 178                         };
 179
 180                         spi: spi {
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183                                 compatible = "intel,ich9-spi";
 184                                 spi-flash@0 {
 185                                         #address-cells = <1>;
 186                                         #size-cells = <1>;
 187                                         reg = <0>;
 188                                         compatible = "stmicro,n25q064a",
 189                                                 "spi-flash";
 190                                         memory-map = <0xff800000 0x00800000>;
 191                                         rw-mrc-cache {
 192                                                 label = "rw-mrc-cache";
 193                                                 reg = <0x006f0000 0x00010000>;
 194                                         };
 195                                 };
 196                         };
 197
 198                         gpioa {
 199                                 compatible = "intel,ich6-gpio";
 200                                 u-boot,dm-pre-reloc;
 201                                 reg = <0 0x20>;
 202                                 bank-name = "A";
 203                                 use-lvl-write-cache;
 204                         };
 205
 206                         gpiob {
 207                                 compatible = "intel,ich6-gpio";
 208                                 u-boot,dm-pre-reloc;
 209                                 reg = <0x20 0x20>;
 210                                 bank-name = "B";
 211                                 use-lvl-write-cache;
 212                         };
 213
 214                         gpioc {
 215                                 compatible = "intel,ich6-gpio";
 216                                 u-boot,dm-pre-reloc;
 217                                 reg = <0x40 0x20>;
 218                                 bank-name = "C";
 219                                 use-lvl-write-cache;
 220                         };
 221
 222                         gpiod {
 223                                 compatible = "intel,ich6-gpio";
 224                                 u-boot,dm-pre-reloc;
 225                                 reg = <0x60 0x20>;
 226                                 bank-name = "D";
 227                                 use-lvl-write-cache;
 228                         };
 229
 230                         gpioe {
 231                                 compatible = "intel,ich6-gpio";
 232                                 u-boot,dm-pre-reloc;
 233                                 reg = <0x80 0x20>;
 234                                 bank-name = "E";
 235                                 use-lvl-write-cache;
 236                         };
 237
 238                         gpiof {
 239                                 compatible = "intel,ich6-gpio";
 240                                 u-boot,dm-pre-reloc;
 241                                 reg = <0xA0 0x20>;
 242                                 bank-name = "F";
 243                                 use-lvl-write-cache;
 244                         };
 245                 };
 246         };
 247
 248         fsp {
 249                 compatible = "intel,baytrail-fsp";
 250                 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
 251                 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
 252                 fsp,mrc-init-spd-addr1 = <0xa0>;
 253                 fsp,mrc-init-spd-addr2 = <0xa2>;
 254                 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
 255                 fsp,enable-sdio;
 256                 fsp,enable-sdcard;
 257                 fsp,enable-hsuart1;
 258                 fsp,enable-spi;
 259                 fsp,enable-sata;
 260                 fsp,sata-mode = <SATA_MODE_AHCI>;
 261 #ifdef CONFIG_USB_XHCI_HCD
 262                 fsp,enable-xhci;
 263 #endif
 264                 fsp,lpe-mode = <LPE_MODE_PCI>;
 265                 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 266                 fsp,enable-dma0;
 267                 fsp,enable-dma1;
 268                 fsp,enable-pwm0;
 269                 fsp,enable-pwm1;
 270                 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 271                 fsp,aperture-size = <APERTURE_SIZE_256MB>;
 272                 fsp,gtt-size = <GTT_SIZE_2MB>;
 273                 fsp,scc-mode = <SCC_MODE_PCI>;
 274                 fsp,os-selection = <OS_SELECTION_LINUX>;
 275                 fsp,emmc45-ddr50-enabled;
 276                 fsp,emmc45-retune-timer-value = <8>;
 277                 fsp,enable-igd;
 278                 fsp,enable-memory-down;
 279                 fsp,memory-down-params {
 280                         compatible = "intel,baytrail-fsp-mdp";
 281                         fsp,dram-speed = <DRAM_SPEED_1333MTS>;
 282                         fsp,dram-type = <DRAM_TYPE_DDR3L>;
 283                         fsp,dimm-0-enable;
 284                         fsp,dimm-1-enable;
 285                         fsp,dimm-width = <DIMM_WIDTH_X16>;
 286                         fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
 287                         fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
 288                         fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
 289
 290                         /* These following values might need a re-visit */
 291                         fsp,dimm-tcl = <8>;
 292                         fsp,dimm-trpt-rcd = <8>;
 293                         fsp,dimm-twr = <8>;
 294                         fsp,dimm-twtr = <4>;
 295                         fsp,dimm-trrd = <6>;
 296                         fsp,dimm-trtp = <4>;
 297                         fsp,dimm-tfaw = <22>;
 298                 };
 299         };
 300
 301         microcode {
 302                 update@0 {
 303 #include "microcode/m0130673325.dtsi"
 304                 };
 305                 update@1 {
 306 #include "microcode/m0130679907.dtsi"
 307                 };
 308         };
 309 };