git.sur5r.net Git - u-boot/blob - arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     Intel
   5  */
   6
   7 #ifndef __FSP_CONFIGS_H__
   8 #define __FSP_CONFIGS_H__
   9
  10 #ifndef __ASSEMBLY__
  11 struct fsp_config_data {
  12         struct fsp_cfg_common   common;
  13         struct upd_region       fsp_upd;
  14 };
  15
  16 struct fspinit_rtbuf {
  17         struct common_buf       common; /* FSP common runtime data structure */
  18 };
  19 #endif
  20
  21 /* FSP user configuration settings */
  22
  23 #define MRC_INIT_TSEG_SIZE_1MB          1
  24 #define MRC_INIT_TSEG_SIZE_2MB          2
  25 #define MRC_INIT_TSEG_SIZE_4MB          4
  26 #define MRC_INIT_TSEG_SIZE_8MB          8
  27
  28 #define MRC_INIT_MMIO_SIZE_1024MB       0x400
  29 #define MRC_INIT_MMIO_SIZE_1536MB       0x600
  30 #define MRC_INIT_MMIO_SIZE_2048MB       0x800
  31
  32 #define EMMC_BOOT_MODE_DISABLED         0
  33 #define EMMC_BOOT_MODE_AUTO             1
  34 #define EMMC_BOOT_MODE_EMMC41           2
  35 #define EMMC_BOOT_MODE_EMCC45           3
  36
  37 #define SATA_MODE_IDE                   0
  38 #define SATA_MODE_AHCI                  1
  39
  40 #define IGD_DVMT50_PRE_ALLOC_32MB       0x01
  41 #define IGD_DVMT50_PRE_ALLOC_64MB       0x02
  42 #define IGD_DVMT50_PRE_ALLOC_96MB       0x03
  43 #define IGD_DVMT50_PRE_ALLOC_128MB      0x04
  44 #define IGD_DVMT50_PRE_ALLOC_160MB      0x05
  45 #define IGD_DVMT50_PRE_ALLOC_192MB      0x06
  46 #define IGD_DVMT50_PRE_ALLOC_224MB      0x07
  47 #define IGD_DVMT50_PRE_ALLOC_256MB      0x08
  48 #define IGD_DVMT50_PRE_ALLOC_288MB      0x09
  49 #define IGD_DVMT50_PRE_ALLOC_320MB      0x0a
  50 #define IGD_DVMT50_PRE_ALLOC_352MB      0x0b
  51 #define IGD_DVMT50_PRE_ALLOC_384MB      0x0c
  52 #define IGD_DVMT50_PRE_ALLOC_416MB      0x0d
  53 #define IGD_DVMT50_PRE_ALLOC_448MB      0x0e
  54 #define IGD_DVMT50_PRE_ALLOC_480MB      0x0f
  55 #define IGD_DVMT50_PRE_ALLOC_512MB      0x10
  56
  57 #define APERTURE_SIZE_128MB             1
  58 #define APERTURE_SIZE_256MB             2
  59 #define APERTURE_SIZE_512MB             3
  60
  61 #define GTT_SIZE_1MB                    1
  62 #define GTT_SIZE_2MB                    2
  63
  64 #define OS_SELECTION_ANDROID            1
  65 #define OS_SELECTION_LINUX              4
  66
  67 #define DRAM_SPEED_800MTS               0
  68 #define DRAM_SPEED_1066MTS              1
  69 #define DRAM_SPEED_1333MTS              2
  70 #define DRAM_SPEED_1600MTS              3
  71
  72 #define DRAM_TYPE_DDR3                  0
  73 #define DRAM_TYPE_DDR3L                 1
  74 #define DRAM_TYPE_DDR3ECC               2
  75 #define DRAM_TYPE_LPDDR2                4
  76 #define DRAM_TYPE_LPDDR3                5
  77 #define DRAM_TYPE_DDR4                  6
  78
  79 #define DIMM_WIDTH_X8                   0
  80 #define DIMM_WIDTH_X16                  1
  81 #define DIMM_WIDTH_X32                  2
  82
  83 #define DIMM_DENSITY_1GBIT              0
  84 #define DIMM_DENSITY_2GBIT              1
  85 #define DIMM_DENSITY_4GBIT              2
  86 #define DIMM_DENSITY_8GBIT              3
  87
  88 #define DIMM_BUS_WIDTH_8BITS            0
  89 #define DIMM_BUS_WIDTH_16BITS           1
  90 #define DIMM_BUS_WIDTH_32BITS           2
  91 #define DIMM_BUS_WIDTH_64BITS           3
  92
  93 #define DIMM_SIDES_1RANKS               0
  94 #define DIMM_SIDES_2RANKS               1
  95
  96 #define LPE_MODE_DISABLED               0
  97 #define LPE_MODE_PCI                    1
  98 #define LPE_MODE_ACPI                   2
  99
 100 #define LPSS_SIO_MODE_ACPI              0
 101 #define LPSS_SIO_MODE_PCI               1
 102
 103 #define SCC_MODE_ACPI                   0
 104 #define SCC_MODE_PCI                    1
 105
 106 #endif /* __FSP_CONFIGS_H__ */