git.sur5r.net Git - u-boot/blob - arch/x86/lib/fsp/fsp_dram.c

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/fsp/fsp_support.h>
   9 #include <asm/e820.h>
  10 #include <asm/mrccache.h>
  11 #include <asm/post.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 int dram_init(void)
  16 {
  17         phys_size_t ram_size = 0;
  18         const struct hob_header *hdr;
  19         struct hob_res_desc *res_desc;
  20
  21         hdr = gd->arch.hob_list;
  22         while (!end_of_hob(hdr)) {
  23                 if (hdr->type == HOB_TYPE_RES_DESC) {
  24                         res_desc = (struct hob_res_desc *)hdr;
  25                         if (res_desc->type == RES_SYS_MEM ||
  26                             res_desc->type == RES_MEM_RESERVED) {
  27                                 ram_size += res_desc->len;
  28                         }
  29                 }
  30                 hdr = get_next_hob(hdr);
  31         }
  32
  33         gd->ram_size = ram_size;
  34         post_code(POST_DRAM);
  35
  36 #ifdef CONFIG_ENABLE_MRC_CACHE
  37         gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
  38                                                &gd->arch.mrc_output_len);
  39 #endif
  40
  41         return 0;
  42 }
  43
  44 int dram_init_banksize(void)
  45 {
  46         gd->bd->bi_dram[0].start = 0;
  47         gd->bd->bi_dram[0].size = gd->ram_size;
  48
  49         return 0;
  50 }
  51
  52 /*
  53  * This function looks for the highest region of memory lower than 4GB which
  54  * has enough space for U-Boot where U-Boot is aligned on a page boundary.
  55  * It overrides the default implementation found elsewhere which simply
  56  * picks the end of ram, wherever that may be. The location of the stack,
  57  * the relocation address, and how far U-Boot is moved by relocation are
  58  * set in the global data structure.
  59  */
  60 ulong board_get_usable_ram_top(ulong total_size)
  61 {
  62         return fsp_get_usable_lowmem_top(gd->arch.hob_list);
  63 }
  64
  65 unsigned int install_e820_map(unsigned int max_entries,
  66                               struct e820_entry *entries)
  67 {
  68         unsigned int num_entries = 0;
  69         const struct hob_header *hdr;
  70         struct hob_res_desc *res_desc;
  71
  72         hdr = gd->arch.hob_list;
  73
  74         while (!end_of_hob(hdr)) {
  75                 if (hdr->type == HOB_TYPE_RES_DESC) {
  76                         res_desc = (struct hob_res_desc *)hdr;
  77                         entries[num_entries].addr = res_desc->phys_start;
  78                         entries[num_entries].size = res_desc->len;
  79
  80                         if (res_desc->type == RES_SYS_MEM)
  81                                 entries[num_entries].type = E820_RAM;
  82                         else if (res_desc->type == RES_MEM_RESERVED)
  83                                 entries[num_entries].type = E820_RESERVED;
  84
  85                         num_entries++;
  86                 }
  87                 hdr = get_next_hob(hdr);
  88         }
  89
  90         /* Mark PCIe ECAM address range as reserved */
  91         entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
  92         entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
  93         entries[num_entries].type = E820_RESERVED;
  94         num_entries++;
  95
  96 #ifdef CONFIG_HAVE_ACPI_RESUME
  97         /*
  98          * Everything between U-Boot's stack and ram top needs to be
  99          * reserved in order for ACPI S3 resume to work.
 100          */
 101         entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
 102         entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \
 103                 CONFIG_STACK_SIZE;
 104         entries[num_entries].type = E820_RESERVED;
 105         num_entries++;
 106 #endif
 107
 108         return num_entries;
 109 }