git.sur5r.net Git - u-boot/blob - board/aries/mcvevk/qts/sdram_config.h

   1 /*
   2  * Altera SoCFPGA SDRAM configuration
   3  *
   4  * SPDX-License-Identifier:     BSD-3-Clause
   5  */
   6
   7 #ifndef __SOCFPGA_SDRAM_CONFIG_H__
   8 #define __SOCFPGA_SDRAM_CONFIG_H__
   9
  10 /* SDRAM configuration */
  11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR              0x5A56A
  12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP              0xB00088
  13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH            0x44555
  14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP              0x2C011000
  15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER                0
  16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                 0
  17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN                0
  18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                    0
  19 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                    8
  20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                  2
  21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                 0
  22 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN                1
  23 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT              10
  24 #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH              2
  25 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS               3
  26 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS                10
  27 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                 1
  28 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS                15
  29 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH            8
  30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH              32
  31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                  0
  32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                     0
  33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                    1
  34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                   0
  35 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                  6
  36 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                 6
  37 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                 16
  38 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                 140
  39 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                 5
  40 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD              6
  41 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI             1560
  42 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP               6
  43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR               6
  44 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR              4
  45 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                 4
  46 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                 4
  47 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                 14
  48 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                  20
  49 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                 5
  50 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT          3
  51 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT         512
  52 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
  53 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
  54 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
  55 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                  0
  56 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                 0
  57 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                      0x0
  58 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK            3
  59 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES        0
  60 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES    8
  61 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0       0x20820820
  62 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32      0x8208208
  63 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0        0
  64 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4       0x41041041
  65 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36      0x410410
  66 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY          0x3FFD1088
  67 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
  68 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32        0x01010101
  69 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64        0x0101
  70 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0    0x21084210
  71 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32   0x1EF84
  72 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0     0x2020
  73 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14    0x0
  74 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46    0xF800
  75 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0                0x200
  76 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN                0
  77 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP              0x760210
  78 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                  2
  79 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA           0
  80 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP              0x980543
  81
  82 /* Sequencer auto configuration */
  83 #define RW_MGR_ACTIVATE_0_AND_1 0x0D
  84 #define RW_MGR_ACTIVATE_0_AND_1_WAIT1   0x0E
  85 #define RW_MGR_ACTIVATE_0_AND_1_WAIT2   0x10
  86 #define RW_MGR_ACTIVATE_1       0x0F
  87 #define RW_MGR_CLEAR_DQS_ENABLE 0x49
  88 #define RW_MGR_GUARANTEED_READ  0x4C
  89 #define RW_MGR_GUARANTEED_READ_CONT     0x54
  90 #define RW_MGR_GUARANTEED_WRITE 0x18
  91 #define RW_MGR_GUARANTEED_WRITE_WAIT0   0x1B
  92 #define RW_MGR_GUARANTEED_WRITE_WAIT1   0x1F
  93 #define RW_MGR_GUARANTEED_WRITE_WAIT2   0x19
  94 #define RW_MGR_GUARANTEED_WRITE_WAIT3   0x1D
  95 #define RW_MGR_IDLE     0x00
  96 #define RW_MGR_IDLE_LOOP1       0x7B
  97 #define RW_MGR_IDLE_LOOP2       0x7A
  98 #define RW_MGR_INIT_RESET_0_CKE_0       0x6F
  99 #define RW_MGR_INIT_RESET_1_CKE_0       0x74
 100 #define RW_MGR_LFSR_WR_RD_BANK_0        0x22
 101 #define RW_MGR_LFSR_WR_RD_BANK_0_DATA   0x25
 102 #define RW_MGR_LFSR_WR_RD_BANK_0_DQS    0x24
 103 #define RW_MGR_LFSR_WR_RD_BANK_0_NOP    0x23
 104 #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT   0x32
 105 #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1   0x21
 106 #define RW_MGR_LFSR_WR_RD_DM_BANK_0     0x36
 107 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA        0x39
 108 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
 109 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
 110 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT        0x46
 111 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1        0x35
 112 #define RW_MGR_MRS0_DLL_RESET   0x02
 113 #define RW_MGR_MRS0_DLL_RESET_MIRR      0x08
 114 #define RW_MGR_MRS0_USER        0x07
 115 #define RW_MGR_MRS0_USER_MIRR   0x0C
 116 #define RW_MGR_MRS1     0x03
 117 #define RW_MGR_MRS1_MIRR        0x09
 118 #define RW_MGR_MRS2     0x04
 119 #define RW_MGR_MRS2_MIRR        0x0A
 120 #define RW_MGR_MRS3     0x05
 121 #define RW_MGR_MRS3_MIRR        0x0B
 122 #define RW_MGR_PRECHARGE_ALL    0x12
 123 #define RW_MGR_READ_B2B 0x59
 124 #define RW_MGR_READ_B2B_WAIT1   0x61
 125 #define RW_MGR_READ_B2B_WAIT2   0x6B
 126 #define RW_MGR_REFRESH_ALL      0x14
 127 #define RW_MGR_RETURN   0x01
 128 #define RW_MGR_SGLE_READ        0x7D
 129 #define RW_MGR_ZQCL     0x06
 130
 131 /* Sequencer defines configuration */
 132 #define AFI_RATE_RATIO  1
 133 #define CALIB_LFIFO_OFFSET      7
 134 #define CALIB_VFIFO_OFFSET      5
 135 #define ENABLE_SUPER_QUICK_CALIBRATION  0
 136 #define IO_DELAY_PER_DCHAIN_TAP 25
 137 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP  25
 138 #define IO_DELAY_PER_OPA_TAP    312
 139 #define IO_DLL_CHAIN_LENGTH     8
 140 #define IO_DQDQS_OUT_PHASE_MAX  0
 141 #define IO_DQS_EN_DELAY_MAX     31
 142 #define IO_DQS_EN_DELAY_OFFSET  0
 143 #define IO_DQS_EN_PHASE_MAX     7
 144 #define IO_DQS_IN_DELAY_MAX     31
 145 #define IO_DQS_IN_RESERVE       4
 146 #define IO_DQS_OUT_RESERVE      4
 147 #define IO_IO_IN_DELAY_MAX      31
 148 #define IO_IO_OUT1_DELAY_MAX    31
 149 #define IO_IO_OUT2_DELAY_MAX    0
 150 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS  0
 151 #define MAX_LATENCY_COUNT_WIDTH 5
 152 #define READ_VALID_FIFO_SIZE    16
 153 #define REG_FILE_INIT_SEQ_SIGNATURE     0x55550496
 154 #define RW_MGR_MEM_ADDRESS_MIRRORING    0
 155 #define RW_MGR_MEM_DATA_MASK_WIDTH      4
 156 #define RW_MGR_MEM_DATA_WIDTH   32
 157 #define RW_MGR_MEM_DQ_PER_READ_DQS      8
 158 #define RW_MGR_MEM_DQ_PER_WRITE_DQS     8
 159 #define RW_MGR_MEM_IF_READ_DQS_WIDTH    4
 160 #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH   4
 161 #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM        1
 162 #define RW_MGR_MEM_NUMBER_OF_RANKS      1
 163 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS  1
 164 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
 165 #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
 166 #define TINIT_CNTR0_VAL 99
 167 #define TINIT_CNTR1_VAL 32
 168 #define TINIT_CNTR2_VAL 32
 169 #define TRESET_CNTR0_VAL        99
 170 #define TRESET_CNTR1_VAL        99
 171 #define TRESET_CNTR2_VAL        10
 172
 173 /* Sequencer ac_rom_init configuration */
 174 const u32 ac_rom_init[] = {
 175         0x20700000,
 176         0x20780000,
 177         0x10080421,
 178         0x10080520,
 179         0x10090044,
 180         0x100a0008,
 181         0x100b0000,
 182         0x10380400,
 183         0x10080441,
 184         0x100804c0,
 185         0x100a0024,
 186         0x10090010,
 187         0x100b0000,
 188         0x30780000,
 189         0x38780000,
 190         0x30780000,
 191         0x10680000,
 192         0x106b0000,
 193         0x10280400,
 194         0x10480000,
 195         0x1c980000,
 196         0x1c9b0000,
 197         0x1c980008,
 198         0x1c9b0008,
 199         0x38f80000,
 200         0x3cf80000,
 201         0x38780000,
 202         0x18180000,
 203         0x18980000,
 204         0x13580000,
 205         0x135b0000,
 206         0x13580008,
 207         0x135b0008,
 208         0x33780000,
 209         0x10580008,
 210         0x10780000
 211 };
 212
 213 /* Sequencer inst_rom_init configuration */
 214 const u32 inst_rom_init[] = {
 215         0x80000,
 216         0x80680,
 217         0x8180,
 218         0x8200,
 219         0x8280,
 220         0x8300,
 221         0x8380,
 222         0x8100,
 223         0x8480,
 224         0x8500,
 225         0x8580,
 226         0x8600,
 227         0x8400,
 228         0x800,
 229         0x8680,
 230         0x880,
 231         0xa680,
 232         0x80680,
 233         0x900,
 234         0x80680,
 235         0x980,
 236         0xa680,
 237         0x8680,
 238         0x80680,
 239         0xb68,
 240         0xcce8,
 241         0xae8,
 242         0x8ce8,
 243         0xb88,
 244         0xec88,
 245         0xa08,
 246         0xac88,
 247         0x80680,
 248         0xce00,
 249         0xcd80,
 250         0xe700,
 251         0xc00,
 252         0x20ce0,
 253         0x20ce0,
 254         0x20ce0,
 255         0x20ce0,
 256         0xd00,
 257         0x680,
 258         0x680,
 259         0x680,
 260         0x680,
 261         0x60e80,
 262         0x61080,
 263         0x61080,
 264         0x61080,
 265         0xa680,
 266         0x8680,
 267         0x80680,
 268         0xce00,
 269         0xcd80,
 270         0xe700,
 271         0xc00,
 272         0x30ce0,
 273         0x30ce0,
 274         0x30ce0,
 275         0x30ce0,
 276         0xd00,
 277         0x680,
 278         0x680,
 279         0x680,
 280         0x680,
 281         0x70e80,
 282         0x71080,
 283         0x71080,
 284         0x71080,
 285         0xa680,
 286         0x8680,
 287         0x80680,
 288         0x1158,
 289         0x6d8,
 290         0x80680,
 291         0x1168,
 292         0x7e8,
 293         0x7e8,
 294         0x87e8,
 295         0x40fe8,
 296         0x410e8,
 297         0x410e8,
 298         0x410e8,
 299         0x1168,
 300         0x7e8,
 301         0x7e8,
 302         0xa7e8,
 303         0x80680,
 304         0x40e88,
 305         0x41088,
 306         0x41088,
 307         0x41088,
 308         0x40f68,
 309         0x410e8,
 310         0x410e8,
 311         0x410e8,
 312         0xa680,
 313         0x40fe8,
 314         0x410e8,
 315         0x410e8,
 316         0x410e8,
 317         0x41008,
 318         0x41088,
 319         0x41088,
 320         0x41088,
 321         0x1100,
 322         0xc680,
 323         0x8680,
 324         0xe680,
 325         0x80680,
 326         0x0,
 327         0x8000,
 328         0xa000,
 329         0xc000,
 330         0x80000,
 331         0x80,
 332         0x8080,
 333         0xa080,
 334         0xc080,
 335         0x80080,
 336         0x9180,
 337         0x8680,
 338         0xa680,
 339         0x80680,
 340         0x40f08,
 341         0x80680
 342 };
 343
 344 #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */