2 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
3 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
6 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/iomux-mx53.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/mx5_video.h>
25 #include <fsl_esdhc.h>
28 #include <ipu_pixfmt.h>
31 #include <dm/platform_data/serial_mxc.h>
34 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
35 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
36 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
37 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
38 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
39 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
40 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
41 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
42 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
43 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
44 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
45 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
46 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
47 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
48 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
51 #define CCAT_BASE_ADDR ((void *)0xf0000000)
52 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
53 #define CCAT_SIZE 1191788
54 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
55 static const char CCAT_SIGNATURE[] = "CCAT";
57 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
58 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
60 DECLARE_GLOBAL_DATA_PTR;
62 u32 get_board_rev(void)
64 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
65 struct fuse_bank *bank = &iim->bank[0];
66 struct fuse_bank0_regs *fuse =
67 (struct fuse_bank0_regs *)bank->fuse_regs;
69 int rev = readl(&fuse->gp[6]);
71 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
76 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
78 void weim_cs0_settings(u32 mode)
80 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
82 writel(0x0, &weim_regs->cs0gcr1);
83 writel(mode, &weim_regs->cs0gcr1);
84 writel(0x00001002, &weim_regs->cs0gcr2);
86 writel(0x04000000, &weim_regs->cs0rcr1);
87 writel(0x00000000, &weim_regs->cs0rcr2);
89 writel(0x04000000, &weim_regs->cs0wcr1);
90 writel(0x00000000, &weim_regs->cs0wcr2);
93 static void setup_gpio_eim(void)
95 gpio_direction_input(GPIO_C3_STATUS);
96 gpio_direction_input(GPIO_C3_DONE);
97 gpio_direction_output(GPIO_C3_CONFIG, 1);
99 weim_cs0_settings(CCAT_MODE_RUN);
102 static void setup_gpio_sups(void)
104 gpio_direction_input(GPIO_SUPS_INT);
106 static const int BLINK_INTERVALL = 50000;
108 while (gpio_get_value(GPIO_SUPS_INT)) {
109 /* signal "CX SUPS power fail" */
110 gpio_set_value(GPIO_LED_PWR_R,
111 (++status / BLINK_INTERVALL) % 2);
114 /* signal "CX power up" */
115 gpio_set_value(GPIO_LED_PWR_R, 1);
118 static void setup_gpio_leds(void)
120 gpio_direction_output(GPIO_LED_SD2_R, 0);
121 gpio_direction_output(GPIO_LED_SD2_B, 0);
122 gpio_direction_output(GPIO_LED_SD2_G, 0);
123 gpio_direction_output(GPIO_LED_SD1_R, 0);
124 gpio_direction_output(GPIO_LED_SD1_B, 0);
125 gpio_direction_output(GPIO_LED_SD1_G, 0);
126 gpio_direction_output(GPIO_LED_PWR_R, 0);
127 gpio_direction_output(GPIO_LED_PWR_B, 0);
128 gpio_direction_output(GPIO_LED_PWR_G, 0);
131 #ifdef CONFIG_USB_EHCI_MX5
132 int board_ehci_hcd_init(int port)
134 /* request VBUS power enable pin, GPIO7_8 */
135 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
140 #ifdef CONFIG_FSL_ESDHC
141 struct fsl_esdhc_cfg esdhc_cfg[2] = {
142 {MMC_SDHC1_BASE_ADDR},
143 {MMC_SDHC2_BASE_ADDR},
146 int board_mmc_getcd(struct mmc *mmc)
148 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
151 gpio_direction_input(GPIO_SD1_CD);
152 gpio_direction_input(GPIO_SD2_CD);
154 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
155 ret = !gpio_get_value(GPIO_SD1_CD);
157 ret = !gpio_get_value(GPIO_SD2_CD);
162 int board_mmc_init(bd_t *bis)
167 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
168 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
170 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
177 printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
178 CONFIG_SYS_FSL_ESDHC_NUM);
181 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
190 static int power_init(void)
192 /* nothing to do on CX9020 */
196 static void clock_1GHz(void)
199 u32 ref_clk = MXC_HCLK;
201 * After increasing voltage to 1.25V, we can switch
202 * CPU clock to 1GHz and DDR to 400MHz safely
204 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
206 printf("CPU: Switch CPU clock to 1GHZ failed\n");
208 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
209 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
211 printf("CPU: Switch DDR clock to 400MHz failed\n");
214 int board_early_init_f(void)
225 * Do not overwrite the console
226 * Use always serial for U-Boot console
228 int overwrite_console(void)
235 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
237 mxc_set_sata_internal_clock();
244 puts("Board: Beckhoff CX9020\n");
249 static int ccat_config_fn(int assert_config, int flush, int cookie)
251 /* prepare FPGA for programming */
252 weim_cs0_settings(CCAT_MODE_CONFIG);
253 gpio_set_value(GPIO_C3_CONFIG, 0);
255 gpio_set_value(GPIO_C3_CONFIG, 1);
261 static int ccat_status_fn(int cookie)
266 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
268 const uint8_t *const buffer = buf;
272 for (i = 0; i < buf_len; ++i)
273 writeb(buffer[i], CCAT_BASE_ADDR);
275 writeb(0xff, CCAT_BASE_ADDR);
276 writeb(0xff, CCAT_BASE_ADDR);
281 static int ccat_done_fn(int cookie)
283 /* programming complete? */
284 return gpio_get_value(GPIO_C3_DONE);
287 static int ccat_post_fn(int cookie)
289 /* switch to FPGA run mode */
290 weim_cs0_settings(CCAT_MODE_RUN);
291 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
293 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
294 printf("Verifing CCAT firmware failed, signature not found\n");
298 /* signal "CX booting OS" */
299 gpio_set_value(GPIO_LED_PWR_R, 1);
300 gpio_set_value(GPIO_LED_PWR_G, 1);
301 gpio_set_value(GPIO_LED_PWR_B, 0);
305 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
306 .config = ccat_config_fn,
307 .status = ccat_status_fn,
308 .done = ccat_done_fn,
309 .write = ccat_write_fn,
310 .abort = ccat_post_fn,
311 .post = ccat_post_fn,
314 static Altera_desc ccat_fpga = {
315 .family = Altera_CYC2,
316 .iface = passive_serial,
318 .iface_fns = &ccat_fns,
319 .base = CCAT_BASE_ADDR,
322 int board_late_init(void)
328 fpga_add(fpga_altera, &ccat_fpga);