2 * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
4 * Authors: Nikita Kiryanov <nikita@compulab.co.il>
6 * Parsing code based on linux/drivers/video/pxafb.c
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <stdio_dev.h>
15 #include <asm/arch/dss.h>
17 #include <scf0403_lcd.h>
18 #include <asm/arch-omap3/dss.h>
24 DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
27 #define CMAP_ADDR 0x80100000
30 * The frame buffer is allocated before we have the chance to parse user input.
31 * To make sure enough memory is allocated for all resolutions, we define
32 * vl_{col | row} to the maximal resolution supported by OMAP3.
34 vidinfo_t panel_info = {
38 .cmap = (ushort *)CMAP_ADDR,
41 static struct panel_config panel_cfg;
42 static enum display_type lcd_def;
45 * A note on DVI presets;
46 * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
47 * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
48 * support two BMP types with one setting.
50 static const struct panel_config preset_dvi_640X480 = {
51 .lcd_size = PANEL_LCD_SIZE(640, 480),
52 .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
53 .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
54 .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
55 .divisor = 12 | (1 << 16),
56 .data_lines = LCD_INTERFACE_24_BIT,
57 .panel_type = ACTIVE_DISPLAY,
59 .gfx_format = GFXFORMAT_RGB16,
62 static const struct panel_config preset_dvi_800X600 = {
63 .lcd_size = PANEL_LCD_SIZE(800, 600),
64 .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
65 .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
66 .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
67 .divisor = 8 | (1 << 16),
68 .data_lines = LCD_INTERFACE_24_BIT,
69 .panel_type = ACTIVE_DISPLAY,
71 .gfx_format = GFXFORMAT_RGB16,
74 static const struct panel_config preset_dvi_1024X768 = {
75 .lcd_size = PANEL_LCD_SIZE(1024, 768),
76 .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
77 .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
78 .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
79 .divisor = 5 | (1 << 16),
80 .data_lines = LCD_INTERFACE_24_BIT,
81 .panel_type = ACTIVE_DISPLAY,
83 .gfx_format = GFXFORMAT_RGB16,
86 static const struct panel_config preset_dvi_1152X864 = {
87 .lcd_size = PANEL_LCD_SIZE(1152, 864),
88 .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
89 .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
90 .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
91 .divisor = 4 | (1 << 16),
92 .data_lines = LCD_INTERFACE_24_BIT,
93 .panel_type = ACTIVE_DISPLAY,
95 .gfx_format = GFXFORMAT_RGB16,
98 static const struct panel_config preset_dvi_1280X960 = {
99 .lcd_size = PANEL_LCD_SIZE(1280, 960),
100 .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
101 .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
102 .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
103 .divisor = 3 | (1 << 16),
104 .data_lines = LCD_INTERFACE_24_BIT,
105 .panel_type = ACTIVE_DISPLAY,
107 .gfx_format = GFXFORMAT_RGB16,
110 static const struct panel_config preset_dvi_1280X1024 = {
111 .lcd_size = PANEL_LCD_SIZE(1280, 1024),
112 .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
113 .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
114 .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
115 .divisor = 3 | (1 << 16),
116 .data_lines = LCD_INTERFACE_24_BIT,
117 .panel_type = ACTIVE_DISPLAY,
119 .gfx_format = GFXFORMAT_RGB16,
122 static const struct panel_config preset_dataimage_480X800 = {
123 .lcd_size = PANEL_LCD_SIZE(480, 800),
124 .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
125 .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
126 .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
127 .divisor = 10 | (1 << 10),
128 .data_lines = LCD_INTERFACE_18_BIT,
129 .panel_type = ACTIVE_DISPLAY,
131 .gfx_format = GFXFORMAT_RGB16,
135 * set_resolution_params()
137 * Due to usage of multiple display related APIs resolution data is located in
138 * more than one place. This function updates them all.
140 static void set_resolution_params(int x, int y)
142 panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
143 panel_info.vl_col = x;
144 panel_info.vl_row = y;
145 lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
148 static void set_preset(const struct panel_config preset, int x_res, int y_res)
151 set_resolution_params(x_res, y_res);
154 static enum display_type set_dvi_preset(const struct panel_config preset,
155 int x_res, int y_res)
157 set_preset(preset, x_res, y_res);
161 static enum display_type set_dataimage_preset(const struct panel_config preset,
162 int x_res, int y_res)
164 set_preset(preset, x_res, y_res);
169 * parse_mode() - parse the mode parameter of custom lcd settings
171 * @mode: <res_x>x<res_y>
173 * Returns -1 on error, 0 on success.
175 static int parse_mode(const char *mode)
177 unsigned int modelen = strlen(mode);
178 int res_specified = 0;
179 unsigned int xres = 0, yres = 0;
180 int yres_specified = 0;
183 for (i = modelen - 1; i >= 0; i--) {
186 if (!yres_specified) {
187 yres = simple_strtoul(&mode[i + 1], NULL, 0);
201 if (i < 0 && yres_specified) {
202 xres = simple_strtoul(mode, NULL, 0);
208 set_resolution_params(xres, yres);
210 printf("LCD: invalid mode: %s\n", mode);
217 #define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
219 * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
221 * @pixclock: the desired pixel clock
223 * Returns -1 on error, 0 on success.
225 * Handling the pixel_clock:
227 * Pixel clock is defined in the OMAP35x TRM as follows:
229 * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
230 * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
231 * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
233 * In practice, this means that in order to set the
234 * divisor for the desired pixel clock one needs to
235 * solve the following equation:
237 * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
239 * NOTE: the explicit equation above is reduced. Do not
240 * try to infer anything from these numbers.
242 static int parse_pixclock(char *pixclock)
244 int divisor, pixclock_val;
245 char *pixclk_start = pixclock;
247 pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
248 divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
249 /* 0 and 1 are illegal values for PCD */
253 panel_cfg.divisor = divisor | (1 << 16);
254 if (pixclock[0] != '\0') {
255 printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
263 * parse_setting() - parse a single setting of custom lcd parameters
265 * @setting: The custom lcd setting <name>:<value>
267 * Returns -1 on failure, 0 on success.
269 static int parse_setting(char *setting)
272 char *setting_start = setting;
274 if (!strncmp(setting, "mode:", 5)) {
275 return parse_mode(setting + 5);
276 } else if (!strncmp(setting, "pixclock:", 9)) {
277 return parse_pixclock(setting + 9);
278 } else if (!strncmp(setting, "left:", 5)) {
279 num_val = simple_strtoul(setting + 5, &setting, 0);
280 panel_cfg.timing_h |= DSS_HBP(num_val);
281 } else if (!strncmp(setting, "right:", 6)) {
282 num_val = simple_strtoul(setting + 6, &setting, 0);
283 panel_cfg.timing_h |= DSS_HFP(num_val);
284 } else if (!strncmp(setting, "upper:", 6)) {
285 num_val = simple_strtoul(setting + 6, &setting, 0);
286 panel_cfg.timing_v |= DSS_VBP(num_val);
287 } else if (!strncmp(setting, "lower:", 6)) {
288 num_val = simple_strtoul(setting + 6, &setting, 0);
289 panel_cfg.timing_v |= DSS_VFP(num_val);
290 } else if (!strncmp(setting, "hsynclen:", 9)) {
291 num_val = simple_strtoul(setting + 9, &setting, 0);
292 panel_cfg.timing_h |= DSS_HSW(num_val);
293 } else if (!strncmp(setting, "vsynclen:", 9)) {
294 num_val = simple_strtoul(setting + 9, &setting, 0);
295 panel_cfg.timing_v |= DSS_VSW(num_val);
296 } else if (!strncmp(setting, "hsync:", 6)) {
297 if (simple_strtoul(setting + 6, &setting, 0) == 0)
298 panel_cfg.pol_freq |= DSS_IHS;
300 panel_cfg.pol_freq &= ~DSS_IHS;
301 } else if (!strncmp(setting, "vsync:", 6)) {
302 if (simple_strtoul(setting + 6, &setting, 0) == 0)
303 panel_cfg.pol_freq |= DSS_IVS;
305 panel_cfg.pol_freq &= ~DSS_IVS;
306 } else if (!strncmp(setting, "outputen:", 9)) {
307 if (simple_strtoul(setting + 9, &setting, 0) == 0)
308 panel_cfg.pol_freq |= DSS_IEO;
310 panel_cfg.pol_freq &= ~DSS_IEO;
311 } else if (!strncmp(setting, "pixclockpol:", 12)) {
312 if (simple_strtoul(setting + 12, &setting, 0) == 0)
313 panel_cfg.pol_freq |= DSS_IPC;
315 panel_cfg.pol_freq &= ~DSS_IPC;
316 } else if (!strncmp(setting, "active", 6)) {
317 panel_cfg.panel_type = ACTIVE_DISPLAY;
318 return 0; /* Avoid sanity check below */
319 } else if (!strncmp(setting, "passive", 7)) {
320 panel_cfg.panel_type = PASSIVE_DISPLAY;
321 return 0; /* Avoid sanity check below */
322 } else if (!strncmp(setting, "display:", 8)) {
323 if (!strncmp(setting + 8, "dvi", 3)) {
324 lcd_def = DVI_CUSTOM;
325 return 0; /* Avoid sanity check below */
328 printf("LCD: unknown option %s\n", setting_start);
332 if (setting[0] != '\0') {
333 printf("LCD: invalid value for %s\n", setting_start);
341 * env_parse_customlcd() - parse custom lcd params from an environment variable.
343 * @custom_lcd_params: The environment variable containing the lcd params.
345 * Returns -1 on failure, 0 on success.
347 static int parse_customlcd(char *custom_lcd_params)
349 char params_cpy[160];
352 strncpy(params_cpy, custom_lcd_params, 160);
353 setting = strtok(params_cpy, ",");
355 if (parse_setting(setting) < 0)
358 setting = strtok(NULL, ",");
361 /* Currently we don't support changing this via custom lcd params */
362 panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
363 panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
369 * env_parse_displaytype() - parse display type.
371 * Parses the environment variable "displaytype", which contains the
372 * name of the display type or preset, in which case it applies its
375 * Returns the type of display that was specified.
377 static enum display_type env_parse_displaytype(char *displaytype)
379 if (!strncmp(displaytype, "dvi640x480", 10))
380 return set_dvi_preset(preset_dvi_640X480, 640, 480);
381 else if (!strncmp(displaytype, "dvi800x600", 10))
382 return set_dvi_preset(preset_dvi_800X600, 800, 600);
383 else if (!strncmp(displaytype, "dvi1024x768", 11))
384 return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
385 else if (!strncmp(displaytype, "dvi1152x864", 11))
386 return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
387 else if (!strncmp(displaytype, "dvi1280x960", 11))
388 return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
389 else if (!strncmp(displaytype, "dvi1280x1024", 12))
390 return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
391 else if (!strncmp(displaytype, "dataimage480x800", 16))
392 return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
397 void lcd_ctrl_init(void *lcdbase)
399 struct prcm *prcm = (struct prcm *)PRCM_BASE;
401 char *displaytype = env_get("displaytype");
403 if (displaytype == NULL)
406 lcd_def = env_parse_displaytype(displaytype);
407 /* If we did not recognize the preset, check if it's an env variable */
408 if (lcd_def == NONE) {
409 custom_lcd = env_get(displaytype);
410 if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
414 panel_cfg.frame_buffer = lcdbase;
415 omap3_dss_panel_config(&panel_cfg);
417 * Pixel clock is defined with many divisions and only few
418 * multiplications of the system clock. Since DSS FCLK divisor is set
419 * to 16 by default, we need to set it to a smaller value, like 3
420 * (chosen via trial and error).
422 clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
425 #ifdef CONFIG_SCF0403_LCD
426 static void scf0403_enable(void)
428 gpio_direction_output(58, 1);
432 static inline void scf0403_enable(void) {}
435 void lcd_enable(void)
442 gpio_direction_output(54, 0); /* Turn on DVI */
452 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}