git.sur5r.net Git - u-boot/blob - board/isee/igep00x0/spl.c

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0+
   3  */
   4 #include <asm/io.h>
   5 #include <asm/arch/mem.h>
   6 #include <asm/arch/sys_proto.h>
   7 #include <jffs2/load_kernel.h>
   8 #include <linux/mtd/nand.h>
   9 #include "igep00x0.h"
  10
  11 /*
  12  * Routine: get_board_mem_timings
  13  * Description: If we use SPL then there is no x-loader nor config header
  14  * so we have to setup the DDR timings ourself on both banks.
  15  */
  16 void get_board_mem_timings(struct board_sdrc_timings *timings)
  17 {
  18         int mfr, id, err = identify_nand_chip(&mfr, &id);
  19
  20         timings->mr = MICRON_V_MR_165;
  21         if (!err) {
  22                 switch (mfr) {
  23                 case NAND_MFR_HYNIX:
  24                         timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  25                         timings->ctrla = HYNIX_V_ACTIMA_200;
  26                         timings->ctrlb = HYNIX_V_ACTIMB_200;
  27                         break;
  28                 case NAND_MFR_MICRON:
  29                         timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  30                         timings->ctrla = MICRON_V_ACTIMA_200;
  31                         timings->ctrlb = MICRON_V_ACTIMB_200;
  32                         break;
  33                 default:
  34                         /* Should not happen... */
  35                         break;
  36                 }
  37                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  38                 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  39         } else {
  40                 if (get_cpu_family() == CPU_OMAP34XX) {
  41                         timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  42                         timings->ctrla = NUMONYX_V_ACTIMA_165;
  43                         timings->ctrlb = NUMONYX_V_ACTIMB_165;
  44                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  45                 } else {
  46                         timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
  47                         timings->ctrla = NUMONYX_V_ACTIMA_200;
  48                         timings->ctrlb = NUMONYX_V_ACTIMB_200;
  49                         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  50                 }
  51                 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  52         }
  53 }
  54
  55 #ifdef CONFIG_SPL_OS_BOOT
  56 int spl_start_uboot(void)
  57 {
  58         /* break into full u-boot on 'c' */
  59         if (serial_tstc() && serial_getc() == 'c')
  60                 return 1;
  61
  62         return 0;
  63 }
  64 #endif