git.sur5r.net Git - u-boot/blob - board/k+p/kp_imx53/kp_imx53.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/iomux-mx53.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/gpio.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <power/pmic.h>
  19 #include <fsl_pmic.h>
  20 #include "kp_id_rev.h"
  21
  22 #define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
  23 #define PHY_nRST IMX_GPIO_NR(7, 6)
  24 #define BOOSTER_OFF IMX_GPIO_NR(2, 23)
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int dram_init(void)
  29 {
  30         u32 size;
  31
  32         size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  33         gd->ram_size = size;
  34
  35         return 0;
  36 }
  37
  38 int dram_init_banksize(void)
  39 {
  40         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  41         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  42
  43         return 0;
  44 }
  45
  46 u32 get_board_rev(void)
  47 {
  48         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  49         struct fuse_bank *bank = &iim->bank[0];
  50         struct fuse_bank0_regs *fuse =
  51                 (struct fuse_bank0_regs *)bank->fuse_regs;
  52
  53         int rev = readl(&fuse->gp[6]);
  54
  55         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  56 }
  57
  58 #ifdef CONFIG_USB_EHCI_MX5
  59 int board_ehci_hcd_init(int port)
  60 {
  61         gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
  62         gpio_direction_output(VBUS_PWR_EN, 1);
  63         return 0;
  64 }
  65 #endif
  66
  67 #ifdef CONFIG_FSL_ESDHC
  68 struct fsl_esdhc_cfg esdhc_cfg[] = {
  69         {MMC_SDHC3_BASE_ADDR},
  70 };
  71
  72 int board_mmc_getcd(struct mmc *mmc)
  73 {
  74         return 1; /* eMMC is always present */
  75 }
  76
  77 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  78                                  PAD_CTL_PUS_100K_UP)
  79 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  80                                  PAD_CTL_DSE_HIGH)
  81
  82 int board_mmc_init(bd_t *bis)
  83 {
  84         int ret;
  85
  86         static const iomux_v3_cfg_t sd3_pads[] = {
  87                 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
  88                              SD_CMD_PAD_CTRL),
  89                 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
  90                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
  91                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
  92                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
  93                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
  94                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
  95                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
  96                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
  97                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
  98         };
  99
 100         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 101         imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
 102
 103         ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 104         if (ret)
 105                 return ret;
 106
 107         return 0;
 108 }
 109 #endif
 110
 111 static int power_init(void)
 112 {
 113         struct udevice *dev;
 114         int ret;
 115
 116         ret = pmic_get("mc34708", &dev);
 117         if (ret) {
 118                 printf("%s: mc34708 not found !\n", __func__);
 119                 return ret;
 120         }
 121
 122         /* Set VDDGP to 1.110V for 800 MHz on SW1 */
 123         pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
 124                         SWx_1_110V_MC34708);
 125
 126         /* Set VCC as 1.30V on SW2 */
 127         pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
 128                         SWx_1_300V_MC34708);
 129
 130         /* Set global reset timer to 4s */
 131         pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
 132                         TIMER_4S_MC34708);
 133
 134         return ret;
 135 }
 136
 137 static void setup_clocks(void)
 138 {
 139         int ret;
 140         u32 ref_clk = MXC_HCLK;
 141         /*
 142          * CPU clock set to 800MHz and DDR to 400MHz
 143          */
 144         ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK);
 145         if (ret)
 146                 printf("CPU:   Switch CPU clock to 800MHZ failed\n");
 147
 148         ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
 149         ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
 150         if (ret)
 151                 printf("CPU:   Switch DDR clock to 400MHz failed\n");
 152 }
 153
 154 static void setup_ups(void)
 155 {
 156         gpio_request(BOOSTER_OFF, "BOOSTER_OFF");
 157         gpio_direction_output(BOOSTER_OFF, 0);
 158 }
 159
 160 int board_early_init_f(void)
 161 {
 162         return 0;
 163 }
 164
 165 /*
 166  * Do not overwrite the console
 167  * Use always serial for U-Boot console
 168  */
 169 int overwrite_console(void)
 170 {
 171         return 1;
 172 }
 173
 174 int board_init(void)
 175 {
 176         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 177
 178         return 0;
 179 }
 180
 181 void eth_phy_reset(void)
 182 {
 183         gpio_request(PHY_nRST, "PHY_nRST");
 184         gpio_direction_output(PHY_nRST, 1);
 185         udelay(50);
 186         gpio_set_value(PHY_nRST, 0);
 187         udelay(400);
 188         gpio_set_value(PHY_nRST, 1);
 189         udelay(50);
 190 }
 191
 192 int board_late_init(void)
 193 {
 194         int ret = 0;
 195
 196         setup_ups();
 197
 198         if (!power_init())
 199                 setup_clocks();
 200
 201         ret = read_eeprom();
 202         if (ret)
 203                 printf("Error %d reading EEPROM content!\n", ret);
 204
 205         eth_phy_reset();
 206
 207         show_eeprom();
 208         read_board_id();
 209
 210         return ret;
 211 }