4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
61 select SUNXI_GEN_SUN6I
65 prompt "Sunxi SoC Variant"
69 bool "sun4i (Allwinner A10)"
71 select ARM_CORTEX_CPU_IS_UP
72 select SUNXI_GEN_SUN4I
76 bool "sun5i (Allwinner A13)"
78 select ARM_CORTEX_CPU_IS_UP
79 select SUNXI_GEN_SUN4I
83 bool "sun6i (Allwinner A31)"
85 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
87 select ARCH_SUPPORT_PSCI
88 select SUNXI_GEN_SUN6I
90 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93 bool "sun7i (Allwinner A20)"
95 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
97 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN4I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
102 config MACH_SUN8I_A23
103 bool "sun8i (Allwinner A23)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
108 select SUNXI_GEN_SUN6I
110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
112 config MACH_SUN8I_A33
113 bool "sun8i (Allwinner A33)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
122 config MACH_SUN8I_A83T
123 bool "sun8i (Allwinner A83T)"
125 select SUNXI_GEN_SUN6I
129 bool "sun8i (Allwinner H3)"
131 select CPU_V7_HAS_NONSEC
132 select CPU_V7_HAS_VIRT
133 select ARCH_SUPPORT_PSCI
134 select MACH_SUNXI_H3_H5
135 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
137 config MACH_SUN8I_R40
138 bool "sun8i (Allwinner R40)"
140 select SUNXI_GEN_SUN6I
143 bool "sun9i (Allwinner A80)"
145 select SUNXI_HIGH_SRAM
146 select SUNXI_GEN_SUN6I
150 bool "sun50i (Allwinner A64)"
152 select SUNXI_GEN_SUN6I
153 select SUNXI_HIGH_SRAM
156 config MACH_SUN50I_H5
157 bool "sun50i (Allwinner H5)"
159 select MACH_SUNXI_H3_H5
160 select SUNXI_HIGH_SRAM
164 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
167 default y if MACH_SUN8I_A23
168 default y if MACH_SUN8I_A33
169 default y if MACH_SUN8I_A83T
170 default y if MACH_SUNXI_H3_H5
171 default y if MACH_SUN8I_R40
173 config RESERVE_ALLWINNER_BOOT0_HEADER
174 bool "reserve space for Allwinner boot0 header"
175 select ENABLE_ARM_SOC_BOOT0_HOOK
177 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
178 filled with magic values post build. The Allwinner provided boot0
179 blob relies on this information to load and execute U-Boot.
180 Only needed on 64-bit Allwinner boards so far when using boot0.
182 config ARM_BOOT_HOOK_RMR
186 select ENABLE_ARM_SOC_BOOT0_HOOK
188 Insert some ARM32 code at the very beginning of the U-Boot binary
189 which uses an RMR register write to bring the core into AArch64 mode.
190 The very first instruction acts as a switch, since it's carefully
191 chosen to be a NOP in one mode and a branch in the other, so the
192 code would only be executed if not already in AArch64.
193 This allows both the SPL and the U-Boot proper to be entered in
194 either mode and switch to AArch64 if needed.
197 int "sunxi dram type"
198 depends on MACH_SUN8I_A83T
201 Set the dram type, 3: DDR3, 7: LPDDR3
204 int "sunxi dram clock speed"
205 default 792 if MACH_SUN9I
206 default 312 if MACH_SUN6I || MACH_SUN8I
207 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
208 default 672 if MACH_SUN50I
210 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
211 must be a multiple of 24. For the sun9i (A80), the tested values
212 (for DDR3-1600) are 312 to 792.
214 if MACH_SUN5I || MACH_SUN7I
216 int "sunxi mbus clock speed"
219 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
224 int "sunxi dram zq value"
225 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
226 default 127 if MACH_SUN7I
227 default 4145117 if MACH_SUN9I
228 default 3881915 if MACH_SUN50I
230 Set the dram zq value.
233 bool "sunxi dram odt enable"
234 default n if !MACH_SUN8I_A23
235 default y if MACH_SUN8I_A23
236 default y if MACH_SUN50I
238 Select this to enable dram odt (on die termination).
240 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
242 int "sunxi dram emr1 value"
243 default 0 if MACH_SUN4I
244 default 4 if MACH_SUN5I || MACH_SUN7I
246 Set the dram controller emr1 value.
249 hex "sunxi dram tpr3 value"
252 Set the dram controller tpr3 parameter. This parameter configures
253 the delay on the command lane and also phase shifts, which are
254 applied for sampling incoming read data. The default value 0
255 means that no phase/delay adjustments are necessary. Properly
256 configuring this parameter increases reliability at high DRAM
259 config DRAM_DQS_GATING_DELAY
260 hex "sunxi dram dqs_gating_delay value"
263 Set the dram controller dqs_gating_delay parmeter. Each byte
264 encodes the DQS gating delay for each byte lane. The delay
265 granularity is 1/4 cycle. For example, the value 0x05060606
266 means that the delay is 5 quarter-cycles for one lane (1.25
267 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
268 The default value 0 means autodetection. The results of hardware
269 autodetection are not very reliable and depend on the chip
270 temperature (sometimes producing different results on cold start
271 and warm reboot). But the accuracy of hardware autodetection
272 is usually good enough, unless running at really high DRAM
273 clocks speeds (up to 600MHz). If unsure, keep as 0.
276 prompt "sunxi dram timings"
277 default DRAM_TIMINGS_VENDOR_MAGIC
279 Select the timings of the DDR3 chips.
281 config DRAM_TIMINGS_VENDOR_MAGIC
282 bool "Magic vendor timings from Android"
284 The same DRAM timings as in the Allwinner boot0 bootloader.
286 config DRAM_TIMINGS_DDR3_1066F_1333H
287 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
289 Use the timings of the standard JEDEC DDR3-1066F speed bin for
290 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
291 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
292 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
293 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
294 that down binning to DDR3-1066F is supported (because DDR3-1066F
295 uses a bit faster timings than DDR3-1333H).
297 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
298 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
300 Use the timings of the slowest possible JEDEC speed bin for the
301 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
302 DDR3-800E, DDR3-1066G or DDR3-1333J.
309 config DRAM_ODT_CORRECTION
310 int "sunxi dram odt correction value"
313 Set the dram odt correction value (range -255 - 255). In allwinner
314 fex files, this option is found in bits 8-15 of the u32 odt_en variable
315 in the [dram] section. When bit 31 of the odt_en variable is set
316 then the correction is negative. Usually the value for this is 0.
320 default 1008000000 if MACH_SUN4I
321 default 1008000000 if MACH_SUN5I
322 default 1008000000 if MACH_SUN6I
323 default 912000000 if MACH_SUN7I
324 default 1008000000 if MACH_SUN8I
325 default 1008000000 if MACH_SUN9I
326 default 816000000 if MACH_SUN50I
328 config SYS_CONFIG_NAME
329 default "sun4i" if MACH_SUN4I
330 default "sun5i" if MACH_SUN5I
331 default "sun6i" if MACH_SUN6I
332 default "sun7i" if MACH_SUN7I
333 default "sun8i" if MACH_SUN8I
334 default "sun9i" if MACH_SUN9I
335 default "sun50i" if MACH_SUN50I
344 bool "UART0 on MicroSD breakout board"
347 Repurpose the SD card slot for getting access to the UART0 serial
348 console. Primarily useful only for low level u-boot debugging on
349 tablets, where normal UART0 is difficult to access and requires
350 device disassembly and/or soldering. As the SD card can't be used
351 at the same time, the system can be only booted in the FEL mode.
352 Only enable this if you really know what you are doing.
354 config OLD_SUNXI_KERNEL_COMPAT
355 bool "Enable workarounds for booting old kernels"
358 Set this to enable various workarounds for old kernels, this results in
359 sub-optimal settings for newer kernels, only enable if needed.
362 string "MAC power pin"
365 Set the pin used to power the MAC. This takes a string in the format
366 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
369 string "Card detect pin for mmc0"
370 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
373 Set the card detect pin for mmc0, leave empty to not use cd. This
374 takes a string in the format understood by sunxi_name_to_gpio, e.g.
375 PH1 for pin 1 of port H.
378 string "Card detect pin for mmc1"
381 See MMC0_CD_PIN help text.
384 string "Card detect pin for mmc2"
387 See MMC0_CD_PIN help text.
390 string "Card detect pin for mmc3"
393 See MMC0_CD_PIN help text.
396 string "Pins for mmc1"
399 Set the pins used for mmc1, when applicable. This takes a string in the
400 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
403 string "Pins for mmc2"
406 See MMC1_PINS help text.
409 string "Pins for mmc3"
412 See MMC1_PINS help text.
414 config MMC_SUNXI_SLOT_EXTRA
415 int "mmc extra slot number"
418 sunxi builds always enable mmc0, some boards also have a second sdcard
419 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
422 config INITIAL_USB_SCAN_DELAY
423 int "delay initial usb scan by x ms to allow builtin devices to init"
426 Some boards have on board usb devices which need longer than the
427 USB spec's 1 second to connect from board powerup. Set this config
428 option to a non 0 value to add an extra delay before the first usb
432 string "Vbus enable pin for usb0 (otg)"
435 Set the Vbus enable pin for usb0 (otg). This takes a string in the
436 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
439 string "Vbus detect pin for usb0 (otg)"
442 Set the Vbus detect pin for usb0 (otg). This takes a string in the
443 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
446 string "ID detect pin for usb0 (otg)"
449 Set the ID detect pin for usb0 (otg). This takes a string in the
450 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
453 string "Vbus enable pin for usb1 (ehci0)"
454 default "PH6" if MACH_SUN4I || MACH_SUN7I
455 default "PH27" if MACH_SUN6I
457 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
458 a string in the format understood by sunxi_name_to_gpio, e.g.
459 PH1 for pin 1 of port H.
462 string "Vbus enable pin for usb2 (ehci1)"
463 default "PH3" if MACH_SUN4I || MACH_SUN7I
464 default "PH24" if MACH_SUN6I
466 See USB1_VBUS_PIN help text.
469 string "Vbus enable pin for usb3 (ehci2)"
472 See USB1_VBUS_PIN help text.
475 bool "Enable I2C/TWI controller 0"
476 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
477 default n if MACH_SUN6I || MACH_SUN8I
480 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
481 its clock and setting up the bus. This is especially useful on devices
482 with slaves connected to the bus or with pins exposed through e.g. an
483 expansion port/header.
486 bool "Enable I2C/TWI controller 1"
490 See I2C0_ENABLE help text.
493 bool "Enable I2C/TWI controller 2"
497 See I2C0_ENABLE help text.
499 if MACH_SUN6I || MACH_SUN7I
501 bool "Enable I2C/TWI controller 3"
505 See I2C0_ENABLE help text.
510 bool "Enable the PRCM I2C/TWI controller"
511 # This is used for the pmic on H3
512 default y if SY8106A_POWER
515 Set this to y to enable the I2C controller which is part of the PRCM.
520 bool "Enable I2C/TWI controller 4"
524 See I2C0_ENABLE help text.
528 bool "Enable support for gpio-s on axp PMICs"
531 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
534 bool "Enable graphical uboot console on HDMI, LCD or VGA"
535 depends on !MACH_SUN8I_A83T
536 depends on !MACH_SUNXI_H3_H5
537 depends on !MACH_SUN8I_R40
538 depends on !MACH_SUN9I
539 depends on !MACH_SUN50I
542 Say Y here to add support for using a cfb console on the HDMI, LCD
543 or VGA output found on most sunxi devices. See doc/README.video for
544 info on how to select the video output and mode.
547 bool "HDMI output support"
548 depends on VIDEO && !MACH_SUN8I
551 Say Y here to add support for outputting video over HDMI.
554 bool "VGA output support"
555 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
558 Say Y here to add support for outputting video over VGA.
560 config VIDEO_VGA_VIA_LCD
561 bool "VGA via LCD controller support"
562 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
565 Say Y here to add support for external DACs connected to the parallel
566 LCD interface driving a VGA connector, such as found on the
569 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
570 bool "Force sync active high for VGA via LCD controller support"
571 depends on VIDEO_VGA_VIA_LCD
574 Say Y here if you've a board which uses opendrain drivers for the vga
575 hsync and vsync signals. Opendrain drivers cannot generate steep enough
576 positive edges for a stable video output, so on boards with opendrain
577 drivers the sync signals must always be active high.
579 config VIDEO_VGA_EXTERNAL_DAC_EN
580 string "LCD panel power enable pin"
581 depends on VIDEO_VGA_VIA_LCD
584 Set the enable pin for the external VGA DAC. This takes a string in the
585 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
587 config VIDEO_COMPOSITE
588 bool "Composite video output support"
589 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
592 Say Y here to add support for outputting composite video.
594 config VIDEO_LCD_MODE
595 string "LCD panel timing details"
599 LCD panel timing details string, leave empty if there is no LCD panel.
600 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
601 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
602 Also see: http://linux-sunxi.org/LCD
604 config VIDEO_LCD_DCLK_PHASE
605 int "LCD panel display clock phase"
609 Select LCD panel display clock phase shift, range 0-3.
611 config VIDEO_LCD_POWER
612 string "LCD panel power enable pin"
616 Set the power enable pin for the LCD panel. This takes a string in the
617 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
619 config VIDEO_LCD_RESET
620 string "LCD panel reset pin"
624 Set the reset pin for the LCD panel. This takes a string in the format
625 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
627 config VIDEO_LCD_BL_EN
628 string "LCD panel backlight enable pin"
632 Set the backlight enable pin for the LCD panel. This takes a string in the
633 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
636 config VIDEO_LCD_BL_PWM
637 string "LCD panel backlight pwm pin"
641 Set the backlight pwm pin for the LCD panel. This takes a string in the
642 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
644 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
645 bool "LCD panel backlight pwm is inverted"
649 Set this if the backlight pwm output is active low.
651 config VIDEO_LCD_PANEL_I2C
652 bool "LCD panel needs to be configured via i2c"
657 Say y here if the LCD panel needs to be configured via i2c. This
658 will add a bitbang i2c controller using gpios to talk to the LCD.
660 config VIDEO_LCD_PANEL_I2C_SDA
661 string "LCD panel i2c interface SDA pin"
662 depends on VIDEO_LCD_PANEL_I2C
665 Set the SDA pin for the LCD i2c interface. This takes a string in the
666 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
668 config VIDEO_LCD_PANEL_I2C_SCL
669 string "LCD panel i2c interface SCL pin"
670 depends on VIDEO_LCD_PANEL_I2C
673 Set the SCL pin for the LCD i2c interface. This takes a string in the
674 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
677 # Note only one of these may be selected at a time! But hidden choices are
678 # not supported by Kconfig
679 config VIDEO_LCD_IF_PARALLEL
682 config VIDEO_LCD_IF_LVDS
687 prompt "LCD panel support"
690 Select which type of LCD panel to support.
692 config VIDEO_LCD_PANEL_PARALLEL
693 bool "Generic parallel interface LCD panel"
694 select VIDEO_LCD_IF_PARALLEL
696 config VIDEO_LCD_PANEL_LVDS
697 bool "Generic lvds interface LCD panel"
698 select VIDEO_LCD_IF_LVDS
700 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
701 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
702 select VIDEO_LCD_SSD2828
703 select VIDEO_LCD_IF_PARALLEL
705 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
707 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
708 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
709 select VIDEO_LCD_ANX9804
710 select VIDEO_LCD_IF_PARALLEL
711 select VIDEO_LCD_PANEL_I2C
713 Select this for eDP LCD panels with 4 lanes running at 1.62G,
714 connected via an ANX9804 bridge chip.
716 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
717 bool "Hitachi tx18d42vm LCD panel"
718 select VIDEO_LCD_HITACHI_TX18D42VM
719 select VIDEO_LCD_IF_LVDS
721 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
723 config VIDEO_LCD_TL059WV5C0
724 bool "tl059wv5c0 LCD panel"
725 select VIDEO_LCD_PANEL_I2C
726 select VIDEO_LCD_IF_PARALLEL
728 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
729 Aigo M60/M608/M606 tablets.
734 string "SATA power pin"
737 Set the pins used to power the SATA. This takes a string in the
738 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
742 int "GMAC Transmit Clock Delay Chain"
745 Set the GMAC Transmit Clock Delay Chain value.
747 config SPL_STACK_R_ADDR
748 default 0x4fe00000 if MACH_SUN4I
749 default 0x4fe00000 if MACH_SUN5I
750 default 0x4fe00000 if MACH_SUN6I
751 default 0x4fe00000 if MACH_SUN7I
752 default 0x4fe00000 if MACH_SUN8I
753 default 0x2fe00000 if MACH_SUN9I
754 default 0x4fe00000 if MACH_SUN50I