git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33 #include <mmc.h>
  34
  35 #include "../common/board_detect.h"
  36 #include "mux_data.h"
  37
  38 #define board_is_x15()          board_ti_is("BBRDX15_")
  39 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  40                                  !strncmp("B.10", board_ti_get_rev(), 3))
  41 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  42                                  !strncmp("C.00", board_ti_get_rev(), 3))
  43 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  44 #define board_is_am572x_evm_reva3()     \
  45                                 (board_ti_is("AM572PM_") && \
  46                                  !strncmp("A.30", board_ti_get_rev(), 3))
  47 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  48 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  49 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  50
  51 #ifdef CONFIG_DRIVER_TI_CPSW
  52 #include <cpsw.h>
  53 #endif
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  58 /* GPIO 7_11 */
  59 #define GPIO_DDR_VTT_EN 203
  60
  61 /* Touch screen controller to identify the LCD */
  62 #define OSD_TS_FT_BUS_ADDRESS   0
  63 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  64 #define OSD_TS_FT_REG_ID        0xA3
  65 /*
  66  * Touchscreen IDs for various OSD panels
  67  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  68  */
  69 /* Used on newer osd101t2587 Panels */
  70 #define OSD_TS_FT_ID_5x46       0x54
  71 /* Used on older osd101t2045 Panels */
  72 #define OSD_TS_FT_ID_5606       0x08
  73
  74 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  75
  76 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  77 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  78
  79 const struct omap_sysinfo sysinfo = {
  80         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  81 };
  82
  83 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  84         .dmm_lisa_map_3 = 0x80740300,
  85         .is_ma_present  = 0x1
  86 };
  87
  88 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  89         .dmm_lisa_map_3 = 0x80640100,
  90         .is_ma_present  = 0x1
  91 };
  92
  93 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  94         .dmm_lisa_map_2 = 0xc0600200,
  95         .dmm_lisa_map_3 = 0x80600100,
  96         .is_ma_present  = 0x1
  97 };
  98
  99 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 100 {
 101         if (board_is_am571x_idk())
 102                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 103         else if (board_is_am574x_idk())
 104                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 105         else
 106                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 107 }
 108
 109 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 110         .sdram_config_init              = 0x61851b32,
 111         .sdram_config                   = 0x61851b32,
 112         .sdram_config2                  = 0x08000000,
 113         .ref_ctrl                       = 0x000040F1,
 114         .ref_ctrl_final                 = 0x00001035,
 115         .sdram_tim1                     = 0xcccf36ab,
 116         .sdram_tim2                     = 0x308f7fda,
 117         .sdram_tim3                     = 0x409f88a8,
 118         .read_idle_ctrl                 = 0x00050000,
 119         .zq_config                      = 0x5007190b,
 120         .temp_alert_config              = 0x00000000,
 121         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 122         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 123         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 124         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 125         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 126         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 127         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 128         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 129         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 130         .emif_rd_wr_lvl_ctl             = 0x00000000,
 131         .emif_rd_wr_exec_thresh         = 0x00000305
 132 };
 133
 134 /* Ext phy ctrl regs 1-35 */
 135 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 136         0x10040100,
 137         0x00910091,
 138         0x00950095,
 139         0x009B009B,
 140         0x009E009E,
 141         0x00980098,
 142         0x00340034,
 143         0x00350035,
 144         0x00340034,
 145         0x00310031,
 146         0x00340034,
 147         0x007F007F,
 148         0x007F007F,
 149         0x007F007F,
 150         0x007F007F,
 151         0x007F007F,
 152         0x00480048,
 153         0x004A004A,
 154         0x00520052,
 155         0x00550055,
 156         0x00500050,
 157         0x00000000,
 158         0x00600020,
 159         0x40011080,
 160         0x08102040,
 161         0x0,
 162         0x0,
 163         0x0,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0,
 170         0x0
 171 };
 172
 173 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 174         .sdram_config_init              = 0x61851b32,
 175         .sdram_config                   = 0x61851b32,
 176         .sdram_config2                  = 0x08000000,
 177         .ref_ctrl                       = 0x000040F1,
 178         .ref_ctrl_final                 = 0x00001035,
 179         .sdram_tim1                     = 0xcccf36b3,
 180         .sdram_tim2                     = 0x308f7fda,
 181         .sdram_tim3                     = 0x407f88a8,
 182         .read_idle_ctrl                 = 0x00050000,
 183         .zq_config                      = 0x5007190b,
 184         .temp_alert_config              = 0x00000000,
 185         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 186         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 187         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 188         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 189         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 190         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 191         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 192         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 193         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 194         .emif_rd_wr_lvl_ctl             = 0x00000000,
 195         .emif_rd_wr_exec_thresh         = 0x00000305
 196 };
 197
 198 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 199         0x10040100,
 200         0x00910091,
 201         0x00950095,
 202         0x009B009B,
 203         0x009E009E,
 204         0x00980098,
 205         0x00340034,
 206         0x00350035,
 207         0x00340034,
 208         0x00310031,
 209         0x00340034,
 210         0x007F007F,
 211         0x007F007F,
 212         0x007F007F,
 213         0x007F007F,
 214         0x007F007F,
 215         0x00480048,
 216         0x004A004A,
 217         0x00520052,
 218         0x00550055,
 219         0x00500050,
 220         0x00000000,
 221         0x00600020,
 222         0x40011080,
 223         0x08102040,
 224         0x0,
 225         0x0,
 226         0x0,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0,
 233         0x0
 234 };
 235
 236 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 237         .sdram_config_init              = 0x61863332,
 238         .sdram_config                   = 0x61863332,
 239         .sdram_config2                  = 0x08000000,
 240         .ref_ctrl                       = 0x0000514d,
 241         .ref_ctrl_final                 = 0x0000144a,
 242         .sdram_tim1                     = 0xd333887c,
 243         .sdram_tim2                     = 0x30b37fe3,
 244         .sdram_tim3                     = 0x409f8ad8,
 245         .read_idle_ctrl                 = 0x00050000,
 246         .zq_config                      = 0x5007190b,
 247         .temp_alert_config              = 0x00000000,
 248         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 249         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 250         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 251         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 252         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 253         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 254         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 255         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 256         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 257         .emif_rd_wr_lvl_ctl             = 0x00000000,
 258         .emif_rd_wr_exec_thresh         = 0x00000305
 259 };
 260
 261 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 262         .sdram_config_init              = 0x61863332,
 263         .sdram_config                   = 0x61863332,
 264         .sdram_config2                  = 0x08000000,
 265         .ref_ctrl                       = 0x0000514d,
 266         .ref_ctrl_final                 = 0x0000144a,
 267         .sdram_tim1                     = 0xd333887c,
 268         .sdram_tim2                     = 0x30b37fe3,
 269         .sdram_tim3                     = 0x409f8ad8,
 270         .read_idle_ctrl                 = 0x00050000,
 271         .zq_config                      = 0x5007190b,
 272         .temp_alert_config              = 0x00000000,
 273         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 274         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 275         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 276         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 277         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 278         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 279         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 280         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 281         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 282         .emif_rd_wr_lvl_ctl             = 0x00000000,
 283         .emif_rd_wr_exec_thresh         = 0x00000305,
 284         .emif_ecc_ctrl_reg              = 0xD0000001,
 285         .emif_ecc_address_range_1       = 0x3FFF0000,
 286         .emif_ecc_address_range_2       = 0x00000000
 287 };
 288
 289 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 290 {
 291         switch (emif_nr) {
 292         case 1:
 293                 if (board_is_am571x_idk())
 294                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 295                 else if (board_is_am574x_idk())
 296                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 297                 else
 298                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 299                 break;
 300         case 2:
 301                 if (board_is_am574x_idk())
 302                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 303                 else
 304                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 305                 break;
 306         }
 307 }
 308
 309 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 310 {
 311         switch (emif_nr) {
 312         case 1:
 313                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 314                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 315                 break;
 316         case 2:
 317                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 318                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 319                 break;
 320         }
 321 }
 322
 323 struct vcores_data beagle_x15_volts = {
 324         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 325         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 326         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 327         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 328         .mpu.pmic               = &tps659038,
 329         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 330
 331         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 332         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 333         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 334         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 335         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 336         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 337         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 338         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 339         .eve.pmic               = &tps659038,
 340         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 341
 342         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 343         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 344         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 345         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 346         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 347         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 348         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 349         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 350         .gpu.pmic               = &tps659038,
 351         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 352
 353         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 354         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 355         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 356         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 357         .core.pmic              = &tps659038,
 358
 359         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 360         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 361         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 362         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 363         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 364         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 365         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 366         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 367         .iva.pmic               = &tps659038,
 368         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 369 };
 370
 371 struct vcores_data am572x_idk_volts = {
 372         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 373         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 374         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 375         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 376         .mpu.pmic               = &tps659038,
 377         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 378
 379         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 380         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 381         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 382         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 383         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 384         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 385         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 386         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 387         .eve.pmic               = &tps659038,
 388         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 389
 390         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 391         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 392         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 393         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 394         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 395         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 396         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 397         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 398         .gpu.pmic               = &tps659038,
 399         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 400
 401         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 402         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 403         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 404         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 405         .core.pmic              = &tps659038,
 406
 407         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 408         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 409         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 410         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 411         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 412         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 413         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 414         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 415         .iva.pmic               = &tps659038,
 416         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 417 };
 418
 419 struct vcores_data am571x_idk_volts = {
 420         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 421         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 422         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 423         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 424         .mpu.pmic               = &tps659038,
 425         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 426
 427         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 428         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 429         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 430         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 431         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 432         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 433         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 434         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 435         .eve.pmic               = &tps659038,
 436         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 437
 438         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 439         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 440         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 441         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 442         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 443         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 444         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 445         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 446         .gpu.pmic               = &tps659038,
 447         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 448
 449         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 450         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 451         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 452         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 453         .core.pmic              = &tps659038,
 454
 455         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 456         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 457         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 458         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 459         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 460         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 461         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 462         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 463         .iva.pmic               = &tps659038,
 464         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 465 };
 466
 467 int get_voltrail_opp(int rail_offset)
 468 {
 469         int opp;
 470
 471         switch (rail_offset) {
 472         case VOLT_MPU:
 473                 opp = DRA7_MPU_OPP;
 474                 break;
 475         case VOLT_CORE:
 476                 opp = DRA7_CORE_OPP;
 477                 break;
 478         case VOLT_GPU:
 479                 opp = DRA7_GPU_OPP;
 480                 break;
 481         case VOLT_EVE:
 482                 opp = DRA7_DSPEVE_OPP;
 483                 break;
 484         case VOLT_IVA:
 485                 opp = DRA7_IVA_OPP;
 486                 break;
 487         default:
 488                 opp = OPP_NOM;
 489         }
 490
 491         return opp;
 492 }
 493
 494
 495 #ifdef CONFIG_SPL_BUILD
 496 /* No env to setup for SPL */
 497 static inline void setup_board_eeprom_env(void) { }
 498
 499 /* Override function to read eeprom information */
 500 void do_board_detect(void)
 501 {
 502         int rc;
 503
 504         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 505                                   CONFIG_EEPROM_CHIP_ADDRESS);
 506         if (rc)
 507                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 508 }
 509
 510 #else   /* CONFIG_SPL_BUILD */
 511
 512 /* Override function to read eeprom information: actual i2c read done by SPL*/
 513 void do_board_detect(void)
 514 {
 515         char *bname = NULL;
 516         int rc;
 517
 518         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 519                                   CONFIG_EEPROM_CHIP_ADDRESS);
 520         if (rc)
 521                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 522
 523         if (board_is_x15())
 524                 bname = "BeagleBoard X15";
 525         else if (board_is_am572x_evm())
 526                 bname = "AM572x EVM";
 527         else if (board_is_am574x_idk())
 528                 bname = "AM574x IDK";
 529         else if (board_is_am572x_idk())
 530                 bname = "AM572x IDK";
 531         else if (board_is_am571x_idk())
 532                 bname = "AM571x IDK";
 533
 534         if (bname)
 535                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 536                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 537 }
 538
 539 static void setup_board_eeprom_env(void)
 540 {
 541         char *name = "beagle_x15";
 542         int rc;
 543
 544         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 545                                   CONFIG_EEPROM_CHIP_ADDRESS);
 546         if (rc)
 547                 goto invalid_eeprom;
 548
 549         if (board_is_x15()) {
 550                 if (board_is_x15_revb1())
 551                         name = "beagle_x15_revb1";
 552                 else if (board_is_x15_revc())
 553                         name = "beagle_x15_revc";
 554                 else
 555                         name = "beagle_x15";
 556         } else if (board_is_am572x_evm()) {
 557                 if (board_is_am572x_evm_reva3())
 558                         name = "am57xx_evm_reva3";
 559                 else
 560                         name = "am57xx_evm";
 561         } else if (board_is_am574x_idk()) {
 562                 name = "am574x_idk";
 563         } else if (board_is_am572x_idk()) {
 564                 name = "am572x_idk";
 565         } else if (board_is_am571x_idk()) {
 566                 name = "am571x_idk";
 567         } else {
 568                 printf("Unidentified board claims %s in eeprom header\n",
 569                        board_ti_get_name());
 570         }
 571
 572 invalid_eeprom:
 573         set_board_info_env(name);
 574 }
 575
 576 #endif  /* CONFIG_SPL_BUILD */
 577
 578 void vcores_init(void)
 579 {
 580         if (board_is_am572x_idk() || board_is_am574x_idk())
 581                 *omap_vcores = &am572x_idk_volts;
 582         else if (board_is_am571x_idk())
 583                 *omap_vcores = &am571x_idk_volts;
 584         else
 585                 *omap_vcores = &beagle_x15_volts;
 586 }
 587
 588 void hw_data_init(void)
 589 {
 590         *prcm = &dra7xx_prcm;
 591         if (is_dra72x())
 592                 *dplls_data = &dra72x_dplls;
 593         else if (is_dra76x())
 594                 *dplls_data = &dra76x_dplls;
 595         else
 596                 *dplls_data = &dra7xx_dplls;
 597         *ctrl = &dra7xx_ctrl;
 598 }
 599
 600 bool am571x_idk_needs_lcd(void)
 601 {
 602         bool needs_lcd;
 603
 604         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 605         if (gpio_get_value(GPIO_ETH_LCD))
 606                 needs_lcd = false;
 607         else
 608                 needs_lcd = true;
 609
 610         gpio_free(GPIO_ETH_LCD);
 611
 612         return needs_lcd;
 613 }
 614
 615 int board_init(void)
 616 {
 617         gpmc_init();
 618         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 619
 620         return 0;
 621 }
 622
 623 void am57x_idk_lcd_detect(void)
 624 {
 625         int r = -ENODEV;
 626         char *idk_lcd = "no";
 627         uint8_t buf = 0;
 628
 629         /* Only valid for IDKs */
 630         if (board_is_x15() || board_is_am572x_evm())
 631                 return;
 632
 633         /* Only AM571x IDK has gpio control detect.. so check that */
 634         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 635                 goto out;
 636
 637         r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
 638         if (r) {
 639                 printf("%s: Failed to set bus address to %d: %d\n",
 640                        __func__, OSD_TS_FT_BUS_ADDRESS, r);
 641                 goto out;
 642         }
 643         r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
 644         if (r) {
 645                 /* AM572x IDK has no explicit settings for optional LCD kit */
 646                 if (board_is_am571x_idk()) {
 647                         printf("%s: Touch screen detect failed: %d!\n",
 648                                __func__, r);
 649                 }
 650                 goto out;
 651         }
 652
 653         /* Read FT ID */
 654         r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
 655         if (r) {
 656                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 657                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 658                        OSD_TS_FT_REG_ID, r);
 659                 goto out;
 660         }
 661
 662         switch (buf) {
 663         case OSD_TS_FT_ID_5606:
 664                 idk_lcd = "osd101t2045";
 665                 break;
 666         case OSD_TS_FT_ID_5x46:
 667                 idk_lcd = "osd101t2587";
 668                 break;
 669         default:
 670                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 671                        __func__, buf);
 672                 /* we will let default be "no lcd" */
 673         }
 674 out:
 675         env_set("idk_lcd", idk_lcd);
 676         return;
 677 }
 678
 679 int board_late_init(void)
 680 {
 681         setup_board_eeprom_env();
 682         u8 val;
 683
 684         /*
 685          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 686          * This is the POWERHOLD-in-Low behavior.
 687          */
 688         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 689
 690         /*
 691          * Default FIT boot on HS devices. Non FIT images are not allowed
 692          * on HS devices.
 693          */
 694         if (get_device_type() == HS_DEVICE)
 695                 env_set("boot_fit", "1");
 696
 697         /*
 698          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 699          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 700          * PMIC Power off. So to be on the safer side set it back
 701          * to POWERHOLD mode irrespective of the current state.
 702          */
 703         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 704                            &val);
 705         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 706         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 707                             val);
 708
 709         omap_die_id_serial();
 710         omap_set_fastboot_vars();
 711
 712         am57x_idk_lcd_detect();
 713
 714 #if !defined(CONFIG_SPL_BUILD)
 715         board_ti_set_ethaddr(2);
 716 #endif
 717
 718         return 0;
 719 }
 720
 721 void set_muxconf_regs(void)
 722 {
 723         do_set_mux32((*ctrl)->control_padconf_core_base,
 724                      early_padconf, ARRAY_SIZE(early_padconf));
 725 }
 726
 727 #ifdef CONFIG_IODELAY_RECALIBRATION
 728 void recalibrate_iodelay(void)
 729 {
 730         const struct pad_conf_entry *pconf;
 731         const struct iodelay_cfg_entry *iod, *delta_iod;
 732         int pconf_sz, iod_sz, delta_iod_sz = 0;
 733         int ret;
 734
 735         if (board_is_am572x_idk()) {
 736                 pconf = core_padconf_array_essential_am572x_idk;
 737                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 738                 iod = iodelay_cfg_array_am572x_idk;
 739                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 740         } else if (board_is_am574x_idk()) {
 741                 pconf = core_padconf_array_essential_am574x_idk;
 742                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 743                 iod = iodelay_cfg_array_am574x_idk;
 744                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 745         } else if (board_is_am571x_idk()) {
 746                 pconf = core_padconf_array_essential_am571x_idk;
 747                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 748                 iod = iodelay_cfg_array_am571x_idk;
 749                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 750         } else {
 751                 /* Common for X15/GPEVM */
 752                 pconf = core_padconf_array_essential_x15;
 753                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 754                 /* There never was an SR1.0 X15.. So.. */
 755                 if (omap_revision() == DRA752_ES1_1) {
 756                         iod = iodelay_cfg_array_x15_sr1_1;
 757                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 758                 } else {
 759                         /* Since full production should switch to SR2.0  */
 760                         iod = iodelay_cfg_array_x15_sr2_0;
 761                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 762                 }
 763         }
 764
 765         /* Setup I/O isolation */
 766         ret = __recalibrate_iodelay_start();
 767         if (ret)
 768                 goto err;
 769
 770         /* Do the muxing here */
 771         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 772
 773         /* Now do the weird minor deltas that should be safe */
 774         if (board_is_x15() || board_is_am572x_evm()) {
 775                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 776                     board_is_x15_revc()) {
 777                         pconf = core_padconf_array_delta_x15_sr2_0;
 778                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 779                 } else {
 780                         pconf = core_padconf_array_delta_x15_sr1_1;
 781                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 782                 }
 783                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 784         }
 785
 786         if (board_is_am571x_idk()) {
 787                 if (am571x_idk_needs_lcd()) {
 788                         pconf = core_padconf_array_vout_am571x_idk;
 789                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 790                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 791                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 792
 793                 } else {
 794                         pconf = core_padconf_array_icss1eth_am571x_idk;
 795                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 796                 }
 797                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 798         }
 799
 800         /* Setup IOdelay configuration */
 801         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 802         if (delta_iod_sz)
 803                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 804                                      delta_iod_sz);
 805
 806 err:
 807         /* Closeup.. remove isolation */
 808         __recalibrate_iodelay_end(ret);
 809 }
 810 #endif
 811
 812 #if defined(CONFIG_MMC)
 813 int board_mmc_init(bd_t *bis)
 814 {
 815         omap_mmc_init(0, 0, 0, -1, -1);
 816         omap_mmc_init(1, 0, 0, -1, -1);
 817         return 0;
 818 }
 819
 820 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 821         .hw_rev = "rev11",
 822         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 823                             MMC_CAP(UHS_SDR104),
 824         .max_freq = 96000000,
 825 };
 826
 827 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 828         .hw_rev = "rev11",
 829         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 830                             MMC_CAP(UHS_SDR104) |
 831                             MMC_CAP(UHS_SDR50),
 832         .max_freq = 48000000,
 833 };
 834
 835 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 836 {
 837         switch (omap_revision()) {
 838         case DRA752_ES1_0:
 839         case DRA752_ES1_1:
 840                 if (addr == OMAP_HSMMC1_BASE)
 841                         return &am57x_es1_1_mmc1_fixups;
 842                 else
 843                         return &am57x_es1_1_mmc23_fixups;
 844         default:
 845                 return NULL;
 846         }
 847 }
 848 #endif
 849
 850 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 851 int spl_start_uboot(void)
 852 {
 853         /* break into full u-boot on 'c' */
 854         if (serial_tstc() && serial_getc() == 'c')
 855                 return 1;
 856
 857 #ifdef CONFIG_SPL_ENV_SUPPORT
 858         env_init();
 859         env_load();
 860         if (env_get_yesno("boot_os") != 1)
 861                 return 1;
 862 #endif
 863
 864         return 0;
 865 }
 866 #endif
 867
 868 #ifdef CONFIG_USB_DWC3
 869 static struct dwc3_device usb_otg_ss2 = {
 870         .maximum_speed = USB_SPEED_HIGH,
 871         .base = DRA7_USB_OTG_SS2_BASE,
 872         .tx_fifo_resize = false,
 873         .index = 1,
 874 };
 875
 876 static struct dwc3_omap_device usb_otg_ss2_glue = {
 877         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 878         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 879         .index = 1,
 880 };
 881
 882 static struct ti_usb_phy_device usb_phy2_device = {
 883         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 884         .index = 1,
 885 };
 886
 887 int usb_gadget_handle_interrupts(int index)
 888 {
 889         u32 status;
 890
 891         status = dwc3_omap_uboot_interrupt_status(index);
 892         if (status)
 893                 dwc3_uboot_handle_interrupt(index);
 894
 895         return 0;
 896 }
 897 #endif /* CONFIG_USB_DWC3 */
 898
 899 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 900 int board_usb_init(int index, enum usb_init_type init)
 901 {
 902         enable_usb_clocks(index);
 903         switch (index) {
 904         case 0:
 905                 if (init == USB_INIT_DEVICE) {
 906                         printf("port %d can't be used as device\n", index);
 907                         disable_usb_clocks(index);
 908                         return -EINVAL;
 909                 }
 910                 break;
 911         case 1:
 912                 if (init == USB_INIT_DEVICE) {
 913 #ifdef CONFIG_USB_DWC3
 914                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 915                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 916                         ti_usb_phy_uboot_init(&usb_phy2_device);
 917                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 918                         dwc3_uboot_init(&usb_otg_ss2);
 919 #endif
 920                 } else {
 921                         printf("port %d can't be used as host\n", index);
 922                         disable_usb_clocks(index);
 923                         return -EINVAL;
 924                 }
 925
 926                 break;
 927         default:
 928                 printf("Invalid Controller Index\n");
 929         }
 930
 931         return 0;
 932 }
 933
 934 int board_usb_cleanup(int index, enum usb_init_type init)
 935 {
 936 #ifdef CONFIG_USB_DWC3
 937         switch (index) {
 938         case 0:
 939         case 1:
 940                 if (init == USB_INIT_DEVICE) {
 941                         ti_usb_phy_uboot_exit(index);
 942                         dwc3_uboot_exit(index);
 943                         dwc3_omap_uboot_exit(index);
 944                 }
 945                 break;
 946         default:
 947                 printf("Invalid Controller Index\n");
 948         }
 949 #endif
 950         disable_usb_clocks(index);
 951         return 0;
 952 }
 953 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 954
 955 #ifdef CONFIG_DRIVER_TI_CPSW
 956
 957 /* Delay value to add to calibrated value */
 958 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 959 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 960 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 961 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 962 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 963 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 964 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 965 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 966 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 967 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 968
 969 static void cpsw_control(int enabled)
 970 {
 971         /* VTP can be added here */
 972 }
 973
 974 static struct cpsw_slave_data cpsw_slaves[] = {
 975         {
 976                 .slave_reg_ofs  = 0x208,
 977                 .sliver_reg_ofs = 0xd80,
 978                 .phy_addr       = 1,
 979         },
 980         {
 981                 .slave_reg_ofs  = 0x308,
 982                 .sliver_reg_ofs = 0xdc0,
 983                 .phy_addr       = 2,
 984         },
 985 };
 986
 987 static struct cpsw_platform_data cpsw_data = {
 988         .mdio_base              = CPSW_MDIO_BASE,
 989         .cpsw_base              = CPSW_BASE,
 990         .mdio_div               = 0xff,
 991         .channels               = 8,
 992         .cpdma_reg_ofs          = 0x800,
 993         .slaves                 = 1,
 994         .slave_data             = cpsw_slaves,
 995         .ale_reg_ofs            = 0xd00,
 996         .ale_entries            = 1024,
 997         .host_port_reg_ofs      = 0x108,
 998         .hw_stats_reg_ofs       = 0x900,
 999         .bd_ram_ofs             = 0x2000,
1000         .mac_control            = (1 << 5),
1001         .control                = cpsw_control,
1002         .host_port_num          = 0,
1003         .version                = CPSW_CTRL_VERSION_2,
1004 };
1005
1006 static u64 mac_to_u64(u8 mac[6])
1007 {
1008         int i;
1009         u64 addr = 0;
1010
1011         for (i = 0; i < 6; i++) {
1012                 addr <<= 8;
1013                 addr |= mac[i];
1014         }
1015
1016         return addr;
1017 }
1018
1019 static void u64_to_mac(u64 addr, u8 mac[6])
1020 {
1021         mac[5] = addr;
1022         mac[4] = addr >> 8;
1023         mac[3] = addr >> 16;
1024         mac[2] = addr >> 24;
1025         mac[1] = addr >> 32;
1026         mac[0] = addr >> 40;
1027 }
1028
1029 int board_eth_init(bd_t *bis)
1030 {
1031         int ret;
1032         uint8_t mac_addr[6];
1033         uint32_t mac_hi, mac_lo;
1034         uint32_t ctrl_val;
1035         int i;
1036         u64 mac1, mac2;
1037         u8 mac_addr1[6], mac_addr2[6];
1038         int num_macs;
1039
1040         /* try reading mac address from efuse */
1041         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1042         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1043         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1044         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1045         mac_addr[2] = mac_hi & 0xFF;
1046         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1047         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1048         mac_addr[5] = mac_lo & 0xFF;
1049
1050         if (!env_get("ethaddr")) {
1051                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1052
1053                 if (is_valid_ethaddr(mac_addr))
1054                         eth_env_set_enetaddr("ethaddr", mac_addr);
1055         }
1056
1057         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1058         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1059         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1060         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1061         mac_addr[2] = mac_hi & 0xFF;
1062         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1063         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1064         mac_addr[5] = mac_lo & 0xFF;
1065
1066         if (!env_get("eth1addr")) {
1067                 if (is_valid_ethaddr(mac_addr))
1068                         eth_env_set_enetaddr("eth1addr", mac_addr);
1069         }
1070
1071         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1072         ctrl_val |= 0x22;
1073         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1074
1075         /* The phy address for the AM57xx IDK are different than x15 */
1076         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1077             board_is_am574x_idk()) {
1078                 cpsw_data.slave_data[0].phy_addr = 0;
1079                 cpsw_data.slave_data[1].phy_addr = 1;
1080         }
1081
1082         ret = cpsw_register(&cpsw_data);
1083         if (ret < 0)
1084                 printf("Error %d registering CPSW switch\n", ret);
1085
1086         /*
1087          * Export any Ethernet MAC addresses from EEPROM.
1088          * On AM57xx the 2 MAC addresses define the address range
1089          */
1090         board_ti_get_eth_mac_addr(0, mac_addr1);
1091         board_ti_get_eth_mac_addr(1, mac_addr2);
1092
1093         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1094                 mac1 = mac_to_u64(mac_addr1);
1095                 mac2 = mac_to_u64(mac_addr2);
1096
1097                 /* must contain an address range */
1098                 num_macs = mac2 - mac1 + 1;
1099                 /* <= 50 to protect against user programming error */
1100                 if (num_macs > 0 && num_macs <= 50) {
1101                         for (i = 0; i < num_macs; i++) {
1102                                 u64_to_mac(mac1 + i, mac_addr);
1103                                 if (is_valid_ethaddr(mac_addr)) {
1104                                         eth_env_set_enetaddr_by_index("eth",
1105                                                                       i + 2,
1106                                                                       mac_addr);
1107                                 }
1108                         }
1109                 }
1110         }
1111
1112         return ret;
1113 }
1114 #endif
1115
1116 #ifdef CONFIG_BOARD_EARLY_INIT_F
1117 /* VTT regulator enable */
1118 static inline void vtt_regulator_enable(void)
1119 {
1120         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1121                 return;
1122
1123         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1124         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1125 }
1126
1127 int board_early_init_f(void)
1128 {
1129         vtt_regulator_enable();
1130         return 0;
1131 }
1132 #endif
1133
1134 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1135 int ft_board_setup(void *blob, bd_t *bd)
1136 {
1137         ft_cpu_setup(blob, bd);
1138
1139         return 0;
1140 }
1141 #endif
1142
1143 #ifdef CONFIG_SPL_LOAD_FIT
1144 int board_fit_config_name_match(const char *name)
1145 {
1146         if (board_is_x15()) {
1147                 if (board_is_x15_revb1()) {
1148                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1149                                 return 0;
1150                 } else if (board_is_x15_revc()) {
1151                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1152                                 return 0;
1153                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1154                         return 0;
1155                 }
1156         } else if (board_is_am572x_evm() &&
1157                    !strcmp(name, "am57xx-beagle-x15")) {
1158                 return 0;
1159         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1160                 return 0;
1161         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1162                 return 0;
1163         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1164                 return 0;
1165         }
1166
1167         return -1;
1168 }
1169 #endif
1170
1171 #ifdef CONFIG_TI_SECURE_DEVICE
1172 void board_fit_image_post_process(void **p_image, size_t *p_size)
1173 {
1174         secure_boot_verify_image(p_image, p_size);
1175 }
1176
1177 void board_tee_image_process(ulong tee_image, size_t tee_size)
1178 {
1179         secure_tee_install((u32)tee_image);
1180 }
1181
1182 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1183 #endif