git.sur5r.net Git - u-boot/blob - board/warp7/warp7.c

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <asm/io.h>
  16 #include <common.h>
  17 #include <fsl_esdhc.h>
  18 #include <i2c.h>
  19 #include <mmc.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <usb.h>
  22 #include <netdev.h>
  23 #include <power/pmic.h>
  24 #include <power/pfuze3000_pmic.h>
  25 #include "../freescale/common/pfuze.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
  30                         PAD_CTL_HYS)
  31 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |     \
  32                         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  33
  34 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  35         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  36
  37 #ifdef CONFIG_SYS_I2C_MXC
  38 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  39 /* I2C1 for PMIC */
  40 static struct i2c_pads_info i2c_pad_info1 = {
  41         .scl = {
  42                 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
  43                 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
  44                 .gp = IMX_GPIO_NR(4, 8),
  45         },
  46         .sda = {
  47                 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
  48                 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
  49                 .gp = IMX_GPIO_NR(4, 9),
  50         },
  51 };
  52 #endif
  53
  54 int dram_init(void)
  55 {
  56         gd->ram_size = PHYS_SDRAM_SIZE;
  57
  58         return 0;
  59 }
  60
  61 static iomux_v3_cfg_t const wdog_pads[] = {
  62         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  63 };
  64
  65 static iomux_v3_cfg_t const uart1_pads[] = {
  66         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  67         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  68 };
  69
  70 static iomux_v3_cfg_t const usdhc3_pads[] = {
  71         MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81         MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82 };
  83
  84 static void setup_iomux_uart(void)
  85 {
  86         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  87 };
  88
  89 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  90         {USDHC3_BASE_ADDR},
  91 };
  92
  93 int board_mmc_getcd(struct mmc *mmc)
  94 {
  95                 /* Assume uSDHC3 emmc is always present */
  96                 return 1;
  97 }
  98
  99 int board_mmc_init(bd_t *bis)
 100 {
 101         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 102         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 103
 104         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 105 }
 106
 107 int board_early_init_f(void)
 108 {
 109         setup_iomux_uart();
 110
 111         return 0;
 112 }
 113
 114 #ifdef CONFIG_POWER
 115 #define I2C_PMIC       0
 116 static struct pmic *pfuze;
 117 int power_init_board(void)
 118 {
 119         int ret;
 120         unsigned int reg, rev_id;
 121
 122         ret = power_pfuze3000_init(I2C_PMIC);
 123         if (ret)
 124                 return ret;
 125
 126         pfuze = pmic_get("PFUZE3000");
 127         ret = pmic_probe(pfuze);
 128         if (ret)
 129                 return ret;
 130
 131         pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
 132         pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
 133         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 134
 135         /* disable Low Power Mode during standby mode */
 136         pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
 137
 138         return 0;
 139 }
 140 #endif
 141
 142 int board_eth_init(bd_t *bis)
 143 {
 144         int ret = 0;
 145
 146 #ifdef CONFIG_USB_ETHER
 147         ret = usb_eth_initialize(bis);
 148         if (ret < 0)
 149                 printf("Error %d registering USB ether.\n", ret);
 150 #endif
 151
 152         return ret;
 153 }
 154
 155 int board_init(void)
 156 {
 157         /* address of boot parameters */
 158         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 159
 160         #ifdef CONFIG_SYS_I2C_MXC
 161                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 162         #endif
 163
 164         return 0;
 165 }
 166
 167 int checkboard(void)
 168 {
 169         char *mode;
 170
 171         if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
 172                 mode = "secure";
 173         else
 174                 mode = "non-secure";
 175
 176         printf("Board: WARP7 in %s mode\n", mode);
 177
 178         return 0;
 179 }
 180
 181 int board_usb_phy_mode(int port)
 182 {
 183         return USB_INIT_DEVICE;
 184 }
 185
 186 int board_late_init(void)
 187 {
 188         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 189
 190         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 191
 192         set_wdog_reset(wdog);
 193
 194         /*
 195          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 196          * since we use PMIC_PWRON to reset the board.
 197          */
 198         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 199
 200         return 0;
 201 }