git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         uint32_t id;
  31         char *name;
  32 } zynqmp_devices[] = {
  33         {
  34                 .id = 0x10,
  35                 .name = "3eg",
  36         },
  37         {
  38                 .id = 0x11,
  39                 .name = "2eg",
  40         },
  41         {
  42                 .id = 0x20,
  43                 .name = "5ev",
  44         },
  45         {
  46                 .id = 0x21,
  47                 .name = "4ev",
  48         },
  49         {
  50                 .id = 0x30,
  51                 .name = "7ev",
  52         },
  53         {
  54                 .id = 0x38,
  55                 .name = "9eg",
  56         },
  57         {
  58                 .id = 0x39,
  59                 .name = "6eg",
  60         },
  61         {
  62                 .id = 0x40,
  63                 .name = "11eg",
  64         },
  65         {
  66                 .id = 0x50,
  67                 .name = "15eg",
  68         },
  69         {
  70                 .id = 0x58,
  71                 .name = "19eg",
  72         },
  73         {
  74                 .id = 0x59,
  75                 .name = "17eg",
  76         },
  77 };
  78
  79 static int chip_id(void)
  80 {
  81         struct pt_regs regs;
  82         regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  83         regs.regs[1] = 0;
  84         regs.regs[2] = 0;
  85         regs.regs[3] = 0;
  86
  87         smc_call(&regs);
  88
  89         /*
  90          * SMC returns:
  91          * regs[0][31:0]  = status of the operation
  92          * regs[0][63:32] = CSU.IDCODE register
  93          * regs[1][31:0]  = CSU.version register
  94          */
  95         regs.regs[0] = upper_32_bits(regs.regs[0]);
  96         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  97                         ZYNQMP_CSU_IDCODE_SVD_MASK;
  98         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  99
 100         return regs.regs[0];
 101 }
 102
 103 static char *zynqmp_get_silicon_idcode_name(void)
 104 {
 105         uint32_t i, id;
 106
 107         id = chip_id();
 108         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 109                 if (zynqmp_devices[i].id == id)
 110                         return zynqmp_devices[i].name;
 111         }
 112         return "unknown";
 113 }
 114 #endif
 115
 116 int board_early_init_f(void)
 117 {
 118 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 119         zynqmp_pmufw_version();
 120 #endif
 121
 122 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 123         psu_init();
 124 #endif
 125
 126         return 0;
 127 }
 128
 129 #define ZYNQMP_VERSION_SIZE     9
 130
 131 int board_init(void)
 132 {
 133         printf("EL Level:\tEL%d\n", current_el());
 134
 135 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 136     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 137     defined(CONFIG_SPL_BUILD))
 138         if (current_el() != 3) {
 139                 static char version[ZYNQMP_VERSION_SIZE];
 140
 141                 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
 142                 zynqmppl.name = strncat(version,
 143                                         zynqmp_get_silicon_idcode_name(),
 144                                         ZYNQMP_VERSION_SIZE);
 145                 printf("Chip ID:\t%s\n", zynqmppl.name);
 146                 fpga_init();
 147                 fpga_add(fpga_xilinx, &zynqmppl);
 148         }
 149 #endif
 150
 151         return 0;
 152 }
 153
 154 int board_early_init_r(void)
 155 {
 156         u32 val;
 157
 158         val = readl(&crlapb_base->timestamp_ref_ctrl);
 159         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 160
 161         if (current_el() == 3 && !val) {
 162                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 163                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 164                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 165
 166                 /* Program freq register in System counter */
 167                 writel(zynqmp_get_system_timer_freq(),
 168                        &iou_scntr_secure->base_frequency_id_register);
 169                 /* And enable system counter */
 170                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 171                        &iou_scntr_secure->counter_control_register);
 172         }
 173         return 0;
 174 }
 175
 176 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 177 {
 178 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 179     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 180     defined(CONFIG_ZYNQ_EEPROM_BUS)
 181         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 182
 183         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 184                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 185                         ethaddr, 6))
 186                 printf("I2C EEPROM MAC address read failed\n");
 187 #endif
 188
 189         return 0;
 190 }
 191
 192 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 193 int dram_init_banksize(void)
 194 {
 195         fdtdec_setup_memory_banksize();
 196
 197         return 0;
 198 }
 199
 200 int dram_init(void)
 201 {
 202         if (fdtdec_setup_memory_size() != 0)
 203                 return -EINVAL;
 204
 205         return 0;
 206 }
 207 #else
 208 int dram_init(void)
 209 {
 210         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 211
 212         return 0;
 213 }
 214 #endif
 215
 216 void reset_cpu(ulong addr)
 217 {
 218 }
 219
 220 int board_late_init(void)
 221 {
 222         u32 reg = 0;
 223         u8 bootmode;
 224         const char *mode;
 225         char *new_targets;
 226
 227         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 228                 debug("Saved variables - Skipping\n");
 229                 return 0;
 230         }
 231
 232         reg = readl(&crlapb_base->boot_mode);
 233         if (reg >> BOOT_MODE_ALT_SHIFT)
 234                 reg >>= BOOT_MODE_ALT_SHIFT;
 235
 236         bootmode = reg & BOOT_MODES_MASK;
 237
 238         puts("Bootmode: ");
 239         switch (bootmode) {
 240         case USB_MODE:
 241                 puts("USB_MODE\n");
 242                 mode = "usb";
 243                 break;
 244         case JTAG_MODE:
 245                 puts("JTAG_MODE\n");
 246                 mode = "pxe dhcp";
 247                 break;
 248         case QSPI_MODE_24BIT:
 249         case QSPI_MODE_32BIT:
 250                 mode = "qspi0";
 251                 puts("QSPI_MODE\n");
 252                 break;
 253         case EMMC_MODE:
 254                 puts("EMMC_MODE\n");
 255                 mode = "mmc0";
 256                 break;
 257         case SD_MODE:
 258                 puts("SD_MODE\n");
 259                 mode = "mmc0";
 260                 break;
 261         case SD1_LSHFT_MODE:
 262                 puts("LVL_SHFT_");
 263                 /* fall through */
 264         case SD_MODE1:
 265                 puts("SD_MODE1\n");
 266 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 267                 mode = "mmc1";
 268 #else
 269                 mode = "mmc0";
 270 #endif
 271                 break;
 272         case NAND_MODE:
 273                 puts("NAND_MODE\n");
 274                 mode = "nand0";
 275                 break;
 276         default:
 277                 mode = "";
 278                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 279                 break;
 280         }
 281
 282         /*
 283          * One terminating char + one byte for space between mode
 284          * and default boot_targets
 285          */
 286         new_targets = calloc(1, strlen(mode) +
 287                                 strlen(getenv("boot_targets")) + 2);
 288
 289         sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
 290         setenv("boot_targets", new_targets);
 291
 292         return 0;
 293 }
 294
 295 int checkboard(void)
 296 {
 297         puts("Board: Xilinx ZynqMP\n");
 298         return 0;
 299 }
 300
 301 #ifdef CONFIG_USB_DWC3
 302 static struct dwc3_device dwc3_device_data0 = {
 303         .maximum_speed = USB_SPEED_HIGH,
 304         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 305         .dr_mode = USB_DR_MODE_PERIPHERAL,
 306         .index = 0,
 307 };
 308
 309 static struct dwc3_device dwc3_device_data1 = {
 310         .maximum_speed = USB_SPEED_HIGH,
 311         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 312         .dr_mode = USB_DR_MODE_PERIPHERAL,
 313         .index = 1,
 314 };
 315
 316 int usb_gadget_handle_interrupts(int index)
 317 {
 318         dwc3_uboot_handle_interrupt(index);
 319         return 0;
 320 }
 321
 322 int board_usb_init(int index, enum usb_init_type init)
 323 {
 324         debug("%s: index %x\n", __func__, index);
 325
 326 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 327         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 328 #endif
 329
 330         switch (index) {
 331         case 0:
 332                 return dwc3_uboot_init(&dwc3_device_data0);
 333         case 1:
 334                 return dwc3_uboot_init(&dwc3_device_data1);
 335         };
 336
 337         return -1;
 338 }
 339
 340 int board_usb_cleanup(int index, enum usb_init_type init)
 341 {
 342         dwc3_uboot_exit(index);
 343         return 0;
 344 }
 345 #endif