git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <usb.h>
  19 #include <dwc3-uboot.h>
  20 #include <zynqmppl.h>
  21 #include <i2c.h>
  22 #include <g_dnl.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  27     !defined(CONFIG_SPL_BUILD)
  28 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  29
  30 static const struct {
  31         u32 id;
  32         u32 ver;
  33         char *name;
  34 } zynqmp_devices[] = {
  35         {
  36                 .id = 0x10,
  37                 .name = "3eg",
  38         },
  39         {
  40                 .id = 0x10,
  41                 .ver = 0x2c,
  42                 .name = "3cg",
  43         },
  44         {
  45                 .id = 0x11,
  46                 .name = "2eg",
  47         },
  48         {
  49                 .id = 0x11,
  50                 .ver = 0x2c,
  51                 .name = "2cg",
  52         },
  53         {
  54                 .id = 0x20,
  55                 .name = "5ev",
  56         },
  57         {
  58                 .id = 0x20,
  59                 .ver = 0x100,
  60                 .name = "5eg",
  61         },
  62         {
  63                 .id = 0x20,
  64                 .ver = 0x12c,
  65                 .name = "5cg",
  66         },
  67         {
  68                 .id = 0x21,
  69                 .name = "4ev",
  70         },
  71         {
  72                 .id = 0x21,
  73                 .ver = 0x100,
  74                 .name = "4eg",
  75         },
  76         {
  77                 .id = 0x21,
  78                 .ver = 0x12c,
  79                 .name = "4cg",
  80         },
  81         {
  82                 .id = 0x30,
  83                 .name = "7ev",
  84         },
  85         {
  86                 .id = 0x30,
  87                 .ver = 0x100,
  88                 .name = "7eg",
  89         },
  90         {
  91                 .id = 0x30,
  92                 .ver = 0x12c,
  93                 .name = "7cg",
  94         },
  95         {
  96                 .id = 0x38,
  97                 .name = "9eg",
  98         },
  99         {
 100                 .id = 0x38,
 101                 .ver = 0x2c,
 102                 .name = "9cg",
 103         },
 104         {
 105                 .id = 0x39,
 106                 .name = "6eg",
 107         },
 108         {
 109                 .id = 0x39,
 110                 .ver = 0x2c,
 111                 .name = "6cg",
 112         },
 113         {
 114                 .id = 0x40,
 115                 .name = "11eg",
 116         },
 117         { /* For testing purpose only */
 118                 .id = 0x50,
 119                 .ver = 0x2c,
 120                 .name = "15cg",
 121         },
 122         {
 123                 .id = 0x50,
 124                 .name = "15eg",
 125         },
 126         {
 127                 .id = 0x58,
 128                 .name = "19eg",
 129         },
 130         {
 131                 .id = 0x59,
 132                 .name = "17eg",
 133         },
 134         {
 135                 .id = 0x61,
 136                 .name = "21dr",
 137         },
 138         {
 139                 .id = 0x63,
 140                 .name = "23dr",
 141         },
 142         {
 143                 .id = 0x65,
 144                 .name = "25dr",
 145         },
 146         {
 147                 .id = 0x64,
 148                 .name = "27dr",
 149         },
 150         {
 151                 .id = 0x60,
 152                 .name = "28dr",
 153         },
 154         {
 155                 .id = 0x62,
 156                 .name = "29dr",
 157         },
 158 };
 159 #endif
 160
 161 int chip_id(unsigned char id)
 162 {
 163         struct pt_regs regs;
 164         int val = -EINVAL;
 165
 166         if (current_el() != 3) {
 167                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 168                 regs.regs[1] = 0;
 169                 regs.regs[2] = 0;
 170                 regs.regs[3] = 0;
 171
 172                 smc_call(&regs);
 173
 174                 /*
 175                  * SMC returns:
 176                  * regs[0][31:0]  = status of the operation
 177                  * regs[0][63:32] = CSU.IDCODE register
 178                  * regs[1][31:0]  = CSU.version register
 179                  * regs[1][63:32] = CSU.IDCODE2 register
 180                  */
 181                 switch (id) {
 182                 case IDCODE:
 183                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 184                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 185                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 186                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 187                         val = regs.regs[0];
 188                         break;
 189                 case VERSION:
 190                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 191                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 192                         val = regs.regs[1];
 193                         break;
 194                 case IDCODE2:
 195                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 196                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 197                         val = regs.regs[1];
 198                         break;
 199                 default:
 200                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 201                 }
 202         } else {
 203                 switch (id) {
 204                 case IDCODE:
 205                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 206                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 207                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 208                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 209                         break;
 210                 case VERSION:
 211                         val = readl(ZYNQMP_CSU_VER_ADDR);
 212                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 213                         break;
 214                 default:
 215                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 216                 }
 217         }
 218
 219         return val;
 220 }
 221
 222 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 223         !defined(CONFIG_SPL_BUILD)
 224 static char *zynqmp_get_silicon_idcode_name(void)
 225 {
 226         u32 i, id, ver;
 227
 228         id = chip_id(IDCODE);
 229         ver = chip_id(IDCODE2);
 230
 231         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 232                 if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
 233                         return zynqmp_devices[i].name;
 234         }
 235         return "unknown";
 236 }
 237 #endif
 238
 239 int board_early_init_f(void)
 240 {
 241         int ret = 0;
 242 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 243         zynqmp_pmufw_version();
 244 #endif
 245
 246 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 247         ret = psu_init();
 248 #endif
 249
 250         return ret;
 251 }
 252
 253 #define ZYNQMP_VERSION_SIZE     9
 254
 255 int board_init(void)
 256 {
 257         printf("EL Level:\tEL%d\n", current_el());
 258
 259 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 260     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 261     defined(CONFIG_SPL_BUILD))
 262         if (current_el() != 3) {
 263                 static char version[ZYNQMP_VERSION_SIZE];
 264
 265                 strncat(version, "zu", 2);
 266                 zynqmppl.name = strncat(version,
 267                                         zynqmp_get_silicon_idcode_name(),
 268                                         ZYNQMP_VERSION_SIZE - 3);
 269                 printf("Chip ID:\t%s\n", zynqmppl.name);
 270                 fpga_init();
 271                 fpga_add(fpga_xilinx, &zynqmppl);
 272         }
 273 #endif
 274
 275         return 0;
 276 }
 277
 278 int board_early_init_r(void)
 279 {
 280         u32 val;
 281
 282         if (current_el() != 3)
 283                 return 0;
 284
 285         val = readl(&crlapb_base->timestamp_ref_ctrl);
 286         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 287
 288         if (!val) {
 289                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 290                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 291                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 292
 293                 /* Program freq register in System counter */
 294                 writel(zynqmp_get_system_timer_freq(),
 295                        &iou_scntr_secure->base_frequency_id_register);
 296                 /* And enable system counter */
 297                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 298                        &iou_scntr_secure->counter_control_register);
 299         }
 300         return 0;
 301 }
 302
 303 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 304 {
 305 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 306     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 307     defined(CONFIG_ZYNQ_EEPROM_BUS)
 308         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 309
 310         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 311                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 312                         ethaddr, 6))
 313                 printf("I2C EEPROM MAC address read failed\n");
 314 #endif
 315
 316         return 0;
 317 }
 318
 319 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 320                          char * const argv[])
 321 {
 322         int ret = 0;
 323
 324         if (current_el() > 1) {
 325                 smp_kick_all_cpus();
 326                 dcache_disable();
 327                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 328                                     ES_TO_AARCH64);
 329         } else {
 330                 printf("FAIL: current EL is not above EL1\n");
 331                 ret = EINVAL;
 332         }
 333         return ret;
 334 }
 335
 336 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 337 int dram_init_banksize(void)
 338 {
 339         return fdtdec_setup_memory_banksize();
 340 }
 341
 342 int dram_init(void)
 343 {
 344         if (fdtdec_setup_memory_size() != 0)
 345                 return -EINVAL;
 346
 347         return 0;
 348 }
 349 #else
 350 int dram_init(void)
 351 {
 352         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 353
 354         return 0;
 355 }
 356 #endif
 357
 358 void reset_cpu(ulong addr)
 359 {
 360 }
 361
 362 int board_late_init(void)
 363 {
 364         u32 reg = 0;
 365         u8 bootmode;
 366         const char *mode;
 367         char *new_targets;
 368         char *env_targets;
 369         int ret;
 370
 371         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 372                 debug("Saved variables - Skipping\n");
 373                 return 0;
 374         }
 375
 376         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 377         if (ret)
 378                 return -EINVAL;
 379
 380         if (reg >> BOOT_MODE_ALT_SHIFT)
 381                 reg >>= BOOT_MODE_ALT_SHIFT;
 382
 383         bootmode = reg & BOOT_MODES_MASK;
 384
 385         puts("Bootmode: ");
 386         switch (bootmode) {
 387         case USB_MODE:
 388                 puts("USB_MODE\n");
 389                 mode = "usb";
 390                 env_set("modeboot", "usb_dfu_spl");
 391                 break;
 392         case JTAG_MODE:
 393                 puts("JTAG_MODE\n");
 394                 mode = "pxe dhcp";
 395                 env_set("modeboot", "jtagboot");
 396                 break;
 397         case QSPI_MODE_24BIT:
 398         case QSPI_MODE_32BIT:
 399                 mode = "qspi0";
 400                 puts("QSPI_MODE\n");
 401                 env_set("modeboot", "qspiboot");
 402                 break;
 403         case EMMC_MODE:
 404                 puts("EMMC_MODE\n");
 405                 mode = "mmc0";
 406                 env_set("modeboot", "emmcboot");
 407                 break;
 408         case SD_MODE:
 409                 puts("SD_MODE\n");
 410                 mode = "mmc0";
 411                 env_set("modeboot", "sdboot");
 412                 break;
 413         case SD1_LSHFT_MODE:
 414                 puts("LVL_SHFT_");
 415                 /* fall through */
 416         case SD_MODE1:
 417                 puts("SD_MODE1\n");
 418 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 419                 mode = "mmc1";
 420                 env_set("sdbootdev", "1");
 421 #else
 422                 mode = "mmc0";
 423 #endif
 424                 env_set("modeboot", "sdboot");
 425                 break;
 426         case NAND_MODE:
 427                 puts("NAND_MODE\n");
 428                 mode = "nand0";
 429                 env_set("modeboot", "nandboot");
 430                 break;
 431         default:
 432                 mode = "";
 433                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 434                 break;
 435         }
 436
 437         /*
 438          * One terminating char + one byte for space between mode
 439          * and default boot_targets
 440          */
 441         env_targets = env_get("boot_targets");
 442         if (env_targets) {
 443                 new_targets = calloc(1, strlen(mode) +
 444                                      strlen(env_targets) + 2);
 445                 sprintf(new_targets, "%s %s", mode, env_targets);
 446         } else {
 447                 new_targets = calloc(1, strlen(mode) + 2);
 448                 sprintf(new_targets, "%s", mode);
 449         }
 450
 451         env_set("boot_targets", new_targets);
 452
 453         return 0;
 454 }
 455
 456 int checkboard(void)
 457 {
 458         puts("Board: Xilinx ZynqMP\n");
 459         return 0;
 460 }
 461
 462 #ifdef CONFIG_USB_DWC3
 463 static struct dwc3_device dwc3_device_data0 = {
 464         .maximum_speed = USB_SPEED_HIGH,
 465         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 466         .dr_mode = USB_DR_MODE_PERIPHERAL,
 467         .index = 0,
 468 };
 469
 470 static struct dwc3_device dwc3_device_data1 = {
 471         .maximum_speed = USB_SPEED_HIGH,
 472         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 473         .dr_mode = USB_DR_MODE_PERIPHERAL,
 474         .index = 1,
 475 };
 476
 477 int usb_gadget_handle_interrupts(int index)
 478 {
 479         dwc3_uboot_handle_interrupt(index);
 480         return 0;
 481 }
 482
 483 int board_usb_init(int index, enum usb_init_type init)
 484 {
 485         debug("%s: index %x\n", __func__, index);
 486
 487 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 488         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 489 #endif
 490
 491         switch (index) {
 492         case 0:
 493                 return dwc3_uboot_init(&dwc3_device_data0);
 494         case 1:
 495                 return dwc3_uboot_init(&dwc3_device_data1);
 496         };
 497
 498         return -1;
 499 }
 500
 501 int board_usb_cleanup(int index, enum usb_init_type init)
 502 {
 503         dwc3_uboot_exit(index);
 504         return 0;
 505 }
 506 #endif