git.sur5r.net Git - u-boot/blob - configs/zynq_zc770_xm013_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_ARCH_ZYNQ=y
   3 CONFIG_SYS_TEXT_BASE=0x4000000
   4 CONFIG_SPL=y
   5 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
   6 CONFIG_SPL_STACK_R_ADDR=0x200000
   7 # CONFIG_SPL_FAT_SUPPORT is not set
   8 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
   9 CONFIG_DISTRO_DEFAULTS=y
  10 CONFIG_FIT=y
  11 CONFIG_FIT_SIGNATURE=y
  12 CONFIG_FIT_VERBOSE=y
  13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
  14 # CONFIG_DISPLAY_CPUINFO is not set
  15 CONFIG_SPL_STACK_R=y
  16 CONFIG_SPL_OS_BOOT=y
  17 CONFIG_SPL_SPI_LOAD=y
  18 CONFIG_SYS_PROMPT="Zynq> "
  19 # CONFIG_CMD_FLASH is not set
  20 CONFIG_CMD_FPGA_LOADBP=y
  21 CONFIG_CMD_FPGA_LOADFS=y
  22 CONFIG_CMD_FPGA_LOADMK=y
  23 CONFIG_CMD_FPGA_LOADP=y
  24 CONFIG_CMD_GPIO=y
  25 # CONFIG_CMD_SETEXPR is not set
  26 CONFIG_CMD_TFTPPUT=y
  27 CONFIG_CMD_CACHE=y
  28 # CONFIG_SPL_DOS_PARTITION is not set
  29 # CONFIG_SPL_ISO_PARTITION is not set
  30 # CONFIG_SPL_EFI_PARTITION is not set
  31 CONFIG_NET_RANDOM_ETHADDR=y
  32 CONFIG_SPL_DM_SEQ_ALIAS=y
  33 CONFIG_BLK=y
  34 CONFIG_FPGA_XILINX=y
  35 CONFIG_FPGA_ZYNQPL=y
  36 CONFIG_DM_GPIO=y
  37 # CONFIG_MMC is not set
  38 CONFIG_SPI_FLASH=y
  39 CONFIG_SPI_FLASH_BAR=y
  40 CONFIG_SPI_FLASH_MACRONIX=y
  41 CONFIG_SPI_FLASH_SPANSION=y
  42 CONFIG_SPI_FLASH_STMICRO=y
  43 CONFIG_SPI_FLASH_WINBOND=y
  44 CONFIG_PHY_MARVELL=y
  45 CONFIG_PHY_REALTEK=y
  46 CONFIG_PHY_XILINX=y
  47 CONFIG_ZYNQ_GEM=y
  48 CONFIG_ZYNQ_SERIAL=y
  49 CONFIG_ZYNQ_QSPI=y