2 * Copyright (C) 2016 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
13 #include <mach/at91_pmc.h>
14 #include <mach/sama5_sfr.h>
18 * The purpose of this clock is to generate a 480 MHz signal. A different
19 * rate can't be configured.
21 #define UTMI_RATE 480000000
23 static int utmi_clk_enable(struct clk *clk)
25 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
26 struct at91_pmc *pmc = plat->reg_base;
29 u32 utmi_ref_clk_freq;
33 if (readl(&pmc->sr) & AT91_PMC_LOCKU)
37 * If mainck rate is different from 12 MHz, we have to configure the
38 * FREQ field of the SFR_UTMICKTRIM register to generate properly
41 err = clk_get_by_index(clk->dev, 0, &clk_dev);
45 clk_rate = clk_get_rate(&clk_dev);
48 utmi_ref_clk_freq = 0;
51 utmi_ref_clk_freq = 1;
54 utmi_ref_clk_freq = 2;
57 * Not supported on SAMA5D2 but it's not an issue since MAINCK
58 * maximum value is 24 MHz.
61 utmi_ref_clk_freq = 3;
64 printf("UTMICK: unsupported mainck rate\n");
68 if (plat->regmap_sfr) {
69 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
73 tmp &= ~AT91_UTMICKTRIM_FREQ;
74 tmp |= utmi_ref_clk_freq;
75 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
78 } else if (utmi_ref_clk_freq) {
79 printf("UTMICK: sfr node required\n");
83 tmp = readl(&pmc->uckr);
84 tmp |= AT91_PMC_UPLLEN |
87 writel(tmp, &pmc->uckr);
89 while (!(readl(&pmc->sr) & AT91_PMC_LOCKU))
95 static ulong utmi_clk_get_rate(struct clk *clk)
97 /* UTMI clk rate is fixed. */
101 static struct clk_ops utmi_clk_ops = {
102 .enable = utmi_clk_enable,
103 .get_rate = utmi_clk_get_rate,
106 static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
108 struct pmc_platdata *plat = dev_get_platdata(dev);
109 struct udevice *syscon;
111 uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
112 "regmap-sfr", &syscon);
115 plat->regmap_sfr = syscon_get_regmap(syscon);
120 static int utmi_clk_probe(struct udevice *dev)
122 return at91_pmc_core_probe(dev);
125 static const struct udevice_id utmi_clk_match[] = {
126 { .compatible = "atmel,at91sam9x5-clk-utmi" },
130 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
131 .name = "at91sam9x5-utmi-clk",
133 .of_match = utmi_clk_match,
134 .probe = utmi_clk_probe,
135 .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
136 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
137 .ops = &utmi_clk_ops,