git.sur5r.net Git - u-boot/blob - drivers/clk/clk_zynqmp.c

   1 /*
   2  * ZynqMP clock driver
   3  *
   4  * Copyright (C) 2016 Xilinx, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/bitops.h>
  11 #include <clk-uclass.h>
  12 #include <clk.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <dm.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  19 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  20
  21 /* Full power domain clocks */
  22 #define CRF_APB_APLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x00)
  23 #define CRF_APB_DPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x0c)
  24 #define CRF_APB_VPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x18)
  25 #define CRF_APB_PLL_STATUS              (zynqmp_crf_apb_clkc_base + 0x24)
  26 #define CRF_APB_APLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x28)
  27 #define CRF_APB_DPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x2c)
  28 #define CRF_APB_VPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x30)
  29 /* Peripheral clocks */
  30 #define CRF_APB_ACPU_CTRL               (zynqmp_crf_apb_clkc_base + 0x40)
  31 #define CRF_APB_DBG_TRACE_CTRL          (zynqmp_crf_apb_clkc_base + 0x44)
  32 #define CRF_APB_DBG_FPD_CTRL            (zynqmp_crf_apb_clkc_base + 0x48)
  33 #define CRF_APB_DP_VIDEO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x50)
  34 #define CRF_APB_DP_AUDIO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x54)
  35 #define CRF_APB_DP_STC_REF_CTRL         (zynqmp_crf_apb_clkc_base + 0x5c)
  36 #define CRF_APB_DDR_CTRL                (zynqmp_crf_apb_clkc_base + 0x60)
  37 #define CRF_APB_GPU_REF_CTRL            (zynqmp_crf_apb_clkc_base + 0x64)
  38 #define CRF_APB_SATA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x80)
  39 #define CRF_APB_PCIE_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x94)
  40 #define CRF_APB_GDMA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x98)
  41 #define CRF_APB_DPDMA_REF_CTRL          (zynqmp_crf_apb_clkc_base + 0x9c)
  42 #define CRF_APB_TOPSW_MAIN_CTRL         (zynqmp_crf_apb_clkc_base + 0xa0)
  43 #define CRF_APB_TOPSW_LSBUS_CTRL        (zynqmp_crf_apb_clkc_base + 0xa4)
  44 #define CRF_APB_GTGREF0_REF_CTRL        (zynqmp_crf_apb_clkc_base + 0xa8)
  45 #define CRF_APB_DBG_TSTMP_CTRL          (zynqmp_crf_apb_clkc_base + 0xd8)
  46
  47 /* Low power domain clocks */
  48 #define CRL_APB_IOPLL_CTRL              (zynqmp_crl_apb_clkc_base + 0x00)
  49 #define CRL_APB_RPLL_CTRL               (zynqmp_crl_apb_clkc_base + 0x10)
  50 #define CRL_APB_PLL_STATUS              (zynqmp_crl_apb_clkc_base + 0x20)
  51 #define CRL_APB_IOPLL_TO_FPD_CTRL       (zynqmp_crl_apb_clkc_base + 0x24)
  52 #define CRL_APB_RPLL_TO_FPD_CTRL        (zynqmp_crl_apb_clkc_base + 0x28)
  53 /* Peripheral clocks */
  54 #define CRL_APB_USB3_DUAL_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x2c)
  55 #define CRL_APB_GEM0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x30)
  56 #define CRL_APB_GEM1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x34)
  57 #define CRL_APB_GEM2_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x38)
  58 #define CRL_APB_GEM3_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x3c)
  59 #define CRL_APB_USB0_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x40)
  60 #define CRL_APB_USB1_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x44)
  61 #define CRL_APB_QSPI_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x48)
  62 #define CRL_APB_SDIO0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x4c)
  63 #define CRL_APB_SDIO1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x50)
  64 #define CRL_APB_UART0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x54)
  65 #define CRL_APB_UART1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x58)
  66 #define CRL_APB_SPI0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x5c)
  67 #define CRL_APB_SPI1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x60)
  68 #define CRL_APB_CAN0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x64)
  69 #define CRL_APB_CAN1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x68)
  70 #define CRL_APB_CPU_R5_CTRL             (zynqmp_crl_apb_clkc_base + 0x70)
  71 #define CRL_APB_IOU_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x7c)
  72 #define CRL_APB_CSU_PLL_CTRL            (zynqmp_crl_apb_clkc_base + 0x80)
  73 #define CRL_APB_PCAP_CTRL               (zynqmp_crl_apb_clkc_base + 0x84)
  74 #define CRL_APB_LPD_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x88)
  75 #define CRL_APB_LPD_LSBUS_CTRL          (zynqmp_crl_apb_clkc_base + 0x8c)
  76 #define CRL_APB_DBG_LPD_CTRL            (zynqmp_crl_apb_clkc_base + 0x90)
  77 #define CRL_APB_NAND_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x94)
  78 #define CRL_APB_ADMA_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x98)
  79 #define CRL_APB_PL0_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa0)
  80 #define CRL_APB_PL1_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa4)
  81 #define CRL_APB_PL2_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa8)
  82 #define CRL_APB_PL3_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xac)
  83 #define CRL_APB_PL0_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xb4)
  84 #define CRL_APB_PL1_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xbc)
  85 #define CRL_APB_PL2_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xc4)
  86 #define CRL_APB_PL3_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xdc)
  87 #define CRL_APB_GEM_TSU_REF_CTRL        (zynqmp_crl_apb_clkc_base + 0xe0)
  88 #define CRL_APB_DLL_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe4)
  89 #define CRL_APB_AMS_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe8)
  90 #define CRL_APB_I2C0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x100)
  91 #define CRL_APB_I2C1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x104)
  92 #define CRL_APB_TIMESTAMP_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x108)
  93
  94 #define ZYNQ_CLK_MAXDIV         0x3f
  95 #define CLK_CTRL_DIV1_SHIFT     16
  96 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  97 #define CLK_CTRL_DIV0_SHIFT     8
  98 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  99 #define CLK_CTRL_SRCSEL_SHIFT   0
 100 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
 101 #define PLLCTRL_FBDIV_MASK      0x7f00
 102 #define PLLCTRL_FBDIV_SHIFT     8
 103 #define PLLCTRL_RESET_MASK      1
 104 #define PLLCTRL_RESET_SHIFT     0
 105 #define PLLCTRL_BYPASS_MASK     0x8
 106 #define PLLCTRL_BYPASS_SHFT     3
 107 #define PLLCTRL_POST_SRC_SHFT   24
 108 #define PLLCTRL_POST_SRC_MASK   (0x7 << PLLCTRL_POST_SRC_SHFT)
 109
 110
 111 #define NUM_MIO_PINS    77
 112
 113 enum zynqmp_clk {
 114         iopll, rpll,
 115         apll, dpll, vpll,
 116         iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
 117         acpu, acpu_half,
 118         dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
 119         dp_video_ref, dp_audio_ref,
 120         dp_stc_ref, gdma_ref, dpdma_ref,
 121         ddr_ref, sata_ref, pcie_ref,
 122         gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
 123         topsw_main, topsw_lsbus,
 124         gtgref0_ref,
 125         lpd_switch, lpd_lsbus,
 126         usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
 127         cpu_r5, cpu_r5_core,
 128         csu_spb, csu_pll, pcap,
 129         iou_switch,
 130         gem_tsu_ref, gem_tsu,
 131         gem0_ref, gem1_ref, gem2_ref, gem3_ref,
 132         gem0_rx, gem1_rx, gem2_rx, gem3_rx,
 133         qspi_ref,
 134         sdio0_ref, sdio1_ref,
 135         uart0_ref, uart1_ref,
 136         spi0_ref, spi1_ref,
 137         nand_ref,
 138         i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
 139         dll_ref,
 140         adma_ref,
 141         timestamp_ref,
 142         ams_ref,
 143         pl0, pl1, pl2, pl3,
 144         wdt,
 145         clk_max,
 146 };
 147
 148 static const char * const clk_names[clk_max] = {
 149         "iopll", "rpll", "apll", "dpll",
 150         "vpll", "iopll_to_fpd", "rpll_to_fpd",
 151         "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
 152         "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
 153         "dbg_trace", "dbg_tstmp", "dp_video_ref",
 154         "dp_audio_ref", "dp_stc_ref", "gdma_ref",
 155         "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
 156         "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
 157         "topsw_main", "topsw_lsbus", "gtgref0_ref",
 158         "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
 159         "usb1_bus_ref", "usb3_dual_ref", "usb0",
 160         "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
 161         "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
 162         "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
 163         "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
 164         "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
 165         "uart0_ref", "uart1_ref", "spi0_ref",
 166         "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
 167         "can0_ref", "can1_ref", "can0", "can1",
 168         "dll_ref", "adma_ref", "timestamp_ref",
 169         "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
 170 };
 171
 172 struct zynqmp_clk_priv {
 173         unsigned long ps_clk_freq;
 174         unsigned long video_clk;
 175         unsigned long pss_alt_ref_clk;
 176         unsigned long gt_crx_ref_clk;
 177         unsigned long aux_ref_clk;
 178 };
 179
 180 static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
 181 {
 182         switch (id) {
 183         case iopll:
 184                 return CRL_APB_IOPLL_CTRL;
 185         case rpll:
 186                 return CRL_APB_RPLL_CTRL;
 187         case apll:
 188                 return CRF_APB_APLL_CTRL;
 189         case dpll:
 190                 return CRF_APB_DPLL_CTRL;
 191         case vpll:
 192                 return CRF_APB_VPLL_CTRL;
 193         case acpu:
 194                 return CRF_APB_ACPU_CTRL;
 195         case ddr_ref:
 196                 return CRF_APB_DDR_CTRL;
 197         case qspi_ref:
 198                 return CRL_APB_QSPI_REF_CTRL;
 199         case gem0_ref:
 200                 return CRL_APB_GEM0_REF_CTRL;
 201         case gem1_ref:
 202                 return CRL_APB_GEM1_REF_CTRL;
 203         case gem2_ref:
 204                 return CRL_APB_GEM2_REF_CTRL;
 205         case gem3_ref:
 206                 return CRL_APB_GEM3_REF_CTRL;
 207         case uart0_ref:
 208                 return CRL_APB_UART0_REF_CTRL;
 209         case uart1_ref:
 210                 return CRL_APB_UART1_REF_CTRL;
 211         case sdio0_ref:
 212                 return CRL_APB_SDIO0_REF_CTRL;
 213         case sdio1_ref:
 214                 return CRL_APB_SDIO1_REF_CTRL;
 215         case spi0_ref:
 216                 return CRL_APB_SPI0_REF_CTRL;
 217         case spi1_ref:
 218                 return CRL_APB_SPI1_REF_CTRL;
 219         case nand_ref:
 220                 return CRL_APB_NAND_REF_CTRL;
 221         case i2c0_ref:
 222                 return CRL_APB_I2C0_REF_CTRL;
 223         case i2c1_ref:
 224                 return CRL_APB_I2C1_REF_CTRL;
 225         case can0_ref:
 226                 return CRL_APB_CAN0_REF_CTRL;
 227         case can1_ref:
 228                 return CRL_APB_CAN1_REF_CTRL;
 229         default:
 230                 debug("Invalid clk id%d\n", id);
 231         }
 232         return 0;
 233 }
 234
 235 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
 236 {
 237         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 238                       CLK_CTRL_SRCSEL_SHIFT;
 239
 240         switch (srcsel) {
 241         case 2:
 242                 return dpll;
 243         case 3:
 244                 return vpll;
 245         case 0 ... 1:
 246         default:
 247                 return apll;
 248         }
 249 }
 250
 251 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
 252 {
 253         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 254                       CLK_CTRL_SRCSEL_SHIFT;
 255
 256         switch (srcsel) {
 257         case 1:
 258                 return vpll;
 259         case 0:
 260         default:
 261                 return dpll;
 262         }
 263 }
 264
 265 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
 266 {
 267         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 268                       CLK_CTRL_SRCSEL_SHIFT;
 269
 270         switch (srcsel) {
 271         case 2:
 272                 return rpll;
 273         case 3:
 274                 return dpll;
 275         case 0 ... 1:
 276         default:
 277                 return iopll;
 278         }
 279 }
 280
 281 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
 282                                     struct zynqmp_clk_priv *priv,
 283                                     bool is_pre_src)
 284 {
 285         u32 src_sel;
 286
 287         if (is_pre_src)
 288                 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 289                            PLLCTRL_POST_SRC_SHFT;
 290         else
 291                 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 292                            PLLCTRL_POST_SRC_SHFT;
 293
 294         switch (src_sel) {
 295         case 4:
 296                 return priv->video_clk;
 297         case 5:
 298                 return priv->pss_alt_ref_clk;
 299         case 6:
 300                 return priv->aux_ref_clk;
 301         case 7:
 302                 return priv->gt_crx_ref_clk;
 303         case 0 ... 3:
 304         default:
 305         return priv->ps_clk_freq;
 306         }
 307 }
 308
 309 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
 310                                      enum zynqmp_clk id)
 311 {
 312         u32 clk_ctrl, reset, mul;
 313         ulong freq;
 314         int ret;
 315
 316         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 317         if (ret) {
 318                 printf("%s mio read fail\n", __func__);
 319                 return -EIO;
 320         }
 321
 322         if (clk_ctrl & PLLCTRL_BYPASS_MASK)
 323                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
 324         else
 325                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
 326
 327         reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
 328         if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
 329                 return 0;
 330
 331         mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 332
 333         freq *= mul;
 334
 335         if (clk_ctrl & (1 << 16))
 336                 freq /= 2;
 337
 338         return freq;
 339 }
 340
 341 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
 342                                      enum zynqmp_clk id)
 343 {
 344         u32 clk_ctrl, div;
 345         enum zynqmp_clk pll;
 346         int ret;
 347         unsigned long pllrate;
 348
 349         ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
 350         if (ret) {
 351                 printf("%s mio read fail\n", __func__);
 352                 return -EIO;
 353         }
 354
 355         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 356
 357         pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
 358         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 359         if (IS_ERR_VALUE(pllrate))
 360                 return pllrate;
 361
 362         return DIV_ROUND_CLOSEST(pllrate, div);
 363 }
 364
 365 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
 366 {
 367         u32 clk_ctrl, div;
 368         enum zynqmp_clk pll;
 369         int ret;
 370         ulong pllrate;
 371
 372         ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
 373         if (ret) {
 374                 printf("%s mio read fail\n", __func__);
 375                 return -EIO;
 376         }
 377
 378         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 379
 380         pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
 381         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 382         if (IS_ERR_VALUE(pllrate))
 383                 return pllrate;
 384
 385         return DIV_ROUND_CLOSEST(pllrate, div);
 386 }
 387
 388 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
 389                                           enum zynqmp_clk id, bool two_divs)
 390 {
 391         enum zynqmp_clk pll;
 392         u32 clk_ctrl, div0;
 393         u32 div1 = 1;
 394         int ret;
 395         ulong pllrate;
 396
 397         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 398         if (ret) {
 399                 printf("%s mio read fail\n", __func__);
 400                 return -EIO;
 401         }
 402
 403         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 404         if (!div0)
 405                 div0 = 1;
 406
 407         if (two_divs) {
 408                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 409                 if (!div1)
 410                         div1 = 1;
 411         }
 412
 413         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 414         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 415         if (IS_ERR_VALUE(pllrate))
 416                 return pllrate;
 417
 418         return
 419                 DIV_ROUND_CLOSEST(
 420                         DIV_ROUND_CLOSEST(pllrate, div0), div1);
 421 }
 422
 423 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
 424                                                        ulong pll_rate,
 425                                                        u32 *div0, u32 *div1)
 426 {
 427         long new_err, best_err = (long)(~0UL >> 1);
 428         ulong new_rate, best_rate = 0;
 429         u32 d0, d1;
 430
 431         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 432                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 433                         new_rate = DIV_ROUND_CLOSEST(
 434                                         DIV_ROUND_CLOSEST(pll_rate, d0), d1);
 435                         new_err = abs(new_rate - rate);
 436
 437                         if (new_err < best_err) {
 438                                 *div0 = d0;
 439                                 *div1 = d1;
 440                                 best_err = new_err;
 441                                 best_rate = new_rate;
 442                         }
 443                 }
 444         }
 445
 446         return best_rate;
 447 }
 448
 449 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
 450                                           enum zynqmp_clk id, ulong rate,
 451                                           bool two_divs)
 452 {
 453         enum zynqmp_clk pll;
 454         u32 clk_ctrl, div0 = 0, div1 = 0;
 455         ulong pll_rate, new_rate;
 456         u32 reg;
 457         int ret;
 458         u32 mask;
 459
 460         reg = zynqmp_clk_get_register(id);
 461         ret = zynqmp_mmio_read(reg, &clk_ctrl);
 462         if (ret) {
 463                 printf("%s mio read fail\n", __func__);
 464                 return -EIO;
 465         }
 466
 467         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 468         pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
 469         if (IS_ERR_VALUE(pll_rate))
 470                 return pll_rate;
 471
 472         clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
 473         if (two_divs) {
 474                 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
 475                 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
 476                                 &div0, &div1);
 477                 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 478         } else {
 479                 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
 480                 if (div0 > ZYNQ_CLK_MAXDIV)
 481                         div0 = ZYNQ_CLK_MAXDIV;
 482                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 483         }
 484         clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 485
 486         mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
 487                (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
 488
 489         ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
 490         if (ret) {
 491                 printf("%s mio write fail\n", __func__);
 492                 return -EIO;
 493         }
 494
 495         return new_rate;
 496 }
 497
 498 static ulong zynqmp_clk_get_rate(struct clk *clk)
 499 {
 500         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 501         enum zynqmp_clk id = clk->id;
 502         bool two_divs = false;
 503
 504         switch (id) {
 505         case iopll ... vpll:
 506                 return zynqmp_clk_get_pll_rate(priv, id);
 507         case acpu:
 508                 return zynqmp_clk_get_cpu_rate(priv, id);
 509         case ddr_ref:
 510                 return zynqmp_clk_get_ddr_rate(priv);
 511         case gem0_ref ... gem3_ref:
 512         case qspi_ref ... can1_ref:
 513                 two_divs = true;
 514                 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
 515         default:
 516                 return -ENXIO;
 517         }
 518 }
 519
 520 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
 521 {
 522         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 523         enum zynqmp_clk id = clk->id;
 524         bool two_divs = true;
 525
 526         switch (id) {
 527         case gem0_ref ... gem3_ref:
 528         case qspi_ref ... can1_ref:
 529                 return zynqmp_clk_set_peripheral_rate(priv, id,
 530                                                       rate, two_divs);
 531         default:
 532                 return -ENXIO;
 533         }
 534 }
 535
 536 int soc_clk_dump(void)
 537 {
 538         struct udevice *dev;
 539         int i, ret;
 540
 541         ret = uclass_get_device_by_driver(UCLASS_CLK,
 542                 DM_GET_DRIVER(zynqmp_clk), &dev);
 543         if (ret)
 544                 return ret;
 545
 546         printf("clk\t\tfrequency\n");
 547         for (i = 0; i < clk_max; i++) {
 548                 const char *name = clk_names[i];
 549                 if (name) {
 550                         struct clk clk;
 551                         unsigned long rate;
 552
 553                         clk.id = i;
 554                         ret = clk_request(dev, &clk);
 555                         if (ret < 0)
 556                                 return ret;
 557
 558                         rate = clk_get_rate(&clk);
 559
 560                         clk_free(&clk);
 561
 562                         if ((rate == (unsigned long)-ENOSYS) ||
 563                             (rate == (unsigned long)-ENXIO) ||
 564                             (rate == (unsigned long)-EIO))
 565                                 printf("%10s%20s\n", name, "unknown");
 566                         else
 567                                 printf("%10s%20lu\n", name, rate);
 568                 }
 569         }
 570
 571         return 0;
 572 }
 573
 574 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
 575 {
 576         struct clk clk;
 577         int ret;
 578
 579         ret = clk_get_by_name(dev, name, &clk);
 580         if (ret < 0) {
 581                 dev_err(dev, "failed to get %s\n", name);
 582                 return ret;
 583         }
 584
 585         *freq = clk_get_rate(&clk);
 586         if (IS_ERR_VALUE(*freq)) {
 587                 dev_err(dev, "failed to get rate %s\n", name);
 588                 return -EINVAL;
 589         }
 590
 591         return 0;
 592 }
 593 static int zynqmp_clk_probe(struct udevice *dev)
 594 {
 595         int ret;
 596         struct zynqmp_clk_priv *priv = dev_get_priv(dev);
 597
 598         debug("%s\n", __func__);
 599         ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
 600         if (ret < 0)
 601                 return -EINVAL;
 602
 603         ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
 604         if (ret < 0)
 605                 return -EINVAL;
 606
 607         ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
 608                                       &priv->pss_alt_ref_clk);
 609         if (ret < 0)
 610                 return -EINVAL;
 611
 612         ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
 613         if (ret < 0)
 614                 return -EINVAL;
 615
 616         ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
 617                                       &priv->gt_crx_ref_clk);
 618         if (ret < 0)
 619                 return -EINVAL;
 620
 621         return 0;
 622 }
 623
 624 static struct clk_ops zynqmp_clk_ops = {
 625         .set_rate = zynqmp_clk_set_rate,
 626         .get_rate = zynqmp_clk_get_rate,
 627 };
 628
 629 static const struct udevice_id zynqmp_clk_ids[] = {
 630         { .compatible = "xlnx,zynqmp-clkc" },
 631         { }
 632 };
 633
 634 U_BOOT_DRIVER(zynqmp_clk) = {
 635         .name = "zynqmp-clk",
 636         .id = UCLASS_CLK,
 637         .of_match = zynqmp_clk_ids,
 638         .probe = zynqmp_clk_probe,
 639         .ops = &zynqmp_clk_ops,
 640         .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
 641 };