git.sur5r.net Git - u-boot/blob - drivers/cpu/bmips_cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/arch/mips/bcm63xx/cpu.c:
   6  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *      Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <common.h>
  11 #include <cpu.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <asm/io.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #define REV_CHIPID_SHIFT                16
  19 #define REV_CHIPID_MASK                 (0xffff << REV_CHIPID_SHIFT)
  20 #define REV_LONG_CHIPID_SHIFT           12
  21 #define REV_LONG_CHIPID_MASK            (0xfffff << REV_LONG_CHIPID_SHIFT)
  22 #define REV_REVID_SHIFT                 0
  23 #define REV_REVID_MASK                  (0xff << REV_REVID_SHIFT)
  24
  25 #define REG_BCM6328_OTP                 0x62c
  26 #define BCM6328_TP1_DISABLED            BIT(9)
  27
  28 #define REG_BCM6318_STRAP_OVRDBUS       0x900
  29 #define OVRDBUS_6318_FREQ_SHIFT         23
  30 #define OVRDBUS_6318_FREQ_MASK          (0x3 << OVRDBUS_6318_FREQ_SHIFT)
  31
  32 #define REG_BCM6328_MISC_STRAPBUS       0x1a40
  33 #define STRAPBUS_6328_FCVO_SHIFT        7
  34 #define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  35
  36 #define REG_BCM6348_PERF_MIPSPLLCFG     0x34
  37 #define MIPSPLLCFG_6348_M1CPU_SHIFT     6
  38 #define MIPSPLLCFG_6348_M1CPU_MASK      (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
  39 #define MIPSPLLCFG_6348_N2_SHIFT        15
  40 #define MIPSPLLCFG_6348_N2_MASK         (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
  41 #define MIPSPLLCFG_6348_N1_SHIFT        20
  42 #define MIPSPLLCFG_6348_N1_MASK         (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
  43
  44 #define REG_BCM6358_DDR_DMIPSPLLCFG     0x12b8
  45 #define DMIPSPLLCFG_6358_M1_SHIFT       0
  46 #define DMIPSPLLCFG_6358_M1_MASK        (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
  47 #define DMIPSPLLCFG_6358_N1_SHIFT       23
  48 #define DMIPSPLLCFG_6358_N1_MASK        (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
  49 #define DMIPSPLLCFG_6358_N2_SHIFT       29
  50 #define DMIPSPLLCFG_6358_N2_MASK        (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
  51
  52 #define REG_BCM6362_MISC_STRAPBUS       0x1814
  53 #define STRAPBUS_6362_FCVO_SHIFT        1
  54 #define STRAPBUS_6362_FCVO_MASK         (0x1f << STRAPBUS_6362_FCVO_SHIFT)
  55
  56 #define REG_BCM6368_DDR_DMIPSPLLCFG     0x12a0
  57 #define DMIPSPLLCFG_6368_P1_SHIFT       0
  58 #define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
  59 #define DMIPSPLLCFG_6368_P2_SHIFT       4
  60 #define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
  61 #define DMIPSPLLCFG_6368_NDIV_SHIFT     16
  62 #define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
  63 #define REG_BCM6368_DDR_DMIPSPLLDIV     0x12a4
  64 #define DMIPSPLLDIV_6368_MDIV_SHIFT     0
  65 #define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
  66
  67 #define REG_BCM63268_MISC_STRAPBUS      0x1814
  68 #define STRAPBUS_63268_FCVO_SHIFT       21
  69 #define STRAPBUS_63268_FCVO_MASK        (0xf << STRAPBUS_63268_FCVO_SHIFT)
  70
  71 struct bmips_cpu_priv;
  72
  73 struct bmips_cpu_hw {
  74         int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
  75         ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
  76         int (*get_cpu_count)(struct bmips_cpu_priv *);
  77 };
  78
  79 struct bmips_cpu_priv {
  80         void __iomem *regs;
  81         const struct bmips_cpu_hw *hw;
  82 };
  83
  84 /* Specific CPU Ops */
  85 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  86                                 int size)
  87 {
  88         unsigned short cpu_id;
  89         unsigned char cpu_rev;
  90         u32 val;
  91
  92         val = readl_be(priv->regs);
  93         cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  94         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
  95
  96         snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
  97
  98         return 0;
  99 }
 100
 101 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 102                                 int size)
 103 {
 104         unsigned int cpu_id;
 105         unsigned char cpu_rev;
 106         u32 val;
 107
 108         val = readl_be(priv->regs);
 109         cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
 110         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
 111
 112         snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
 113
 114         return 0;
 115 }
 116
 117 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
 118 {
 119         return 333000000;
 120 }
 121
 122 static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
 123 {
 124         unsigned int mips_pll_fcvo;
 125
 126         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
 127         mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
 128                         >> OVRDBUS_6318_FREQ_SHIFT;
 129
 130         switch (mips_pll_fcvo) {
 131         case 0:
 132                 return 166000000;
 133         case 1:
 134                 return 400000000;
 135         case 2:
 136                 return 250000000;
 137         case 3:
 138                 return 333000000;
 139         default:
 140                 return 0;
 141         }
 142 }
 143
 144 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 145 {
 146         unsigned int mips_pll_fcvo;
 147
 148         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
 149         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
 150                         >> STRAPBUS_6328_FCVO_SHIFT;
 151
 152         switch (mips_pll_fcvo) {
 153         case 0x12:
 154         case 0x14:
 155         case 0x19:
 156                 return 160000000;
 157         case 0x1c:
 158                 return 192000000;
 159         case 0x13:
 160         case 0x15:
 161                 return 200000000;
 162         case 0x1a:
 163                 return 384000000;
 164         case 0x16:
 165                 return 400000000;
 166         default:
 167                 return 320000000;
 168         }
 169 }
 170
 171 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
 172 {
 173         return 240000000;
 174 }
 175
 176 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
 177 {
 178         unsigned int tmp, n1, n2, m1;
 179
 180         tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
 181         n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
 182         n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
 183         m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
 184
 185         return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
 186 }
 187
 188 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 189 {
 190         unsigned int tmp, n1, n2, m1;
 191
 192         tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
 193         n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
 194         n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
 195         m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
 196
 197         return (16 * 1000000 * n1 * n2) / m1;
 198 }
 199
 200 static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
 201 {
 202         unsigned int mips_pll_fcvo;
 203
 204         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
 205         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
 206                         >> STRAPBUS_6362_FCVO_SHIFT;
 207
 208         switch (mips_pll_fcvo) {
 209         case 0x03:
 210         case 0x0b:
 211         case 0x13:
 212         case 0x1b:
 213                 return 240000000;
 214         case 0x04:
 215         case 0x0c:
 216         case 0x14:
 217         case 0x1c:
 218                 return 160000000;
 219         case 0x05:
 220         case 0x0e:
 221         case 0x16:
 222         case 0x1e:
 223         case 0x1f:
 224                 return 400000000;
 225         case 0x06:
 226                 return 440000000;
 227         case 0x07:
 228         case 0x17:
 229                 return 384000000;
 230         case 0x15:
 231         case 0x1d:
 232                 return 200000000;
 233         default:
 234                 return 320000000;
 235         }
 236 }
 237
 238 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
 239 {
 240         unsigned int tmp, p1, p2, ndiv, m1;
 241
 242         tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
 243         p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
 244         p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
 245         ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
 246                DMIPSPLLCFG_6368_NDIV_SHIFT;
 247
 248         tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
 249         m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
 250
 251         return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
 252 }
 253
 254 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
 255 {
 256         unsigned int mips_pll_fcvo;
 257
 258         mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
 259         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
 260                         >> STRAPBUS_63268_FCVO_SHIFT;
 261
 262         switch (mips_pll_fcvo) {
 263         case 0x3:
 264         case 0xe:
 265                 return 320000000;
 266         case 0xa:
 267                 return 333000000;
 268         case 0x2:
 269         case 0xb:
 270         case 0xf:
 271                 return 400000000;
 272         default:
 273                 return 0;
 274         }
 275 }
 276
 277 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 278 {
 279         u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
 280
 281         if (val & BCM6328_TP1_DISABLED)
 282                 return 1;
 283         else
 284                 return 2;
 285 }
 286
 287 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
 288 {
 289         return 1;
 290 }
 291
 292 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 293 {
 294         return 2;
 295 }
 296
 297 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
 298         .get_cpu_desc = bmips_short_cpu_desc,
 299         .get_cpu_freq = bcm3380_get_cpu_freq,
 300         .get_cpu_count = bcm6358_get_cpu_count,
 301 };
 302
 303 static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
 304         .get_cpu_desc = bmips_short_cpu_desc,
 305         .get_cpu_freq = bcm6318_get_cpu_freq,
 306         .get_cpu_count = bcm6345_get_cpu_count,
 307 };
 308
 309 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 310         .get_cpu_desc = bmips_long_cpu_desc,
 311         .get_cpu_freq = bcm6328_get_cpu_freq,
 312         .get_cpu_count = bcm6328_get_cpu_count,
 313 };
 314
 315 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
 316         .get_cpu_desc = bmips_short_cpu_desc,
 317         .get_cpu_freq = bcm6338_get_cpu_freq,
 318         .get_cpu_count = bcm6345_get_cpu_count,
 319 };
 320
 321 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
 322         .get_cpu_desc = bmips_short_cpu_desc,
 323         .get_cpu_freq = bcm6348_get_cpu_freq,
 324         .get_cpu_count = bcm6345_get_cpu_count,
 325 };
 326
 327 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 328         .get_cpu_desc = bmips_short_cpu_desc,
 329         .get_cpu_freq = bcm6358_get_cpu_freq,
 330         .get_cpu_count = bcm6358_get_cpu_count,
 331 };
 332
 333 static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
 334         .get_cpu_desc = bmips_short_cpu_desc,
 335         .get_cpu_freq = bcm6362_get_cpu_freq,
 336         .get_cpu_count = bcm6358_get_cpu_count,
 337 };
 338
 339 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
 340         .get_cpu_desc = bmips_short_cpu_desc,
 341         .get_cpu_freq = bcm6368_get_cpu_freq,
 342         .get_cpu_count = bcm6358_get_cpu_count,
 343 };
 344
 345 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
 346         .get_cpu_desc = bmips_long_cpu_desc,
 347         .get_cpu_freq = bcm63268_get_cpu_freq,
 348         .get_cpu_count = bcm6358_get_cpu_count,
 349 };
 350
 351 /* Generic CPU Ops */
 352 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
 353 {
 354         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 355         const struct bmips_cpu_hw *hw = priv->hw;
 356
 357         return hw->get_cpu_desc(priv, buf, size);
 358 }
 359
 360 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 361 {
 362         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 363         const struct bmips_cpu_hw *hw = priv->hw;
 364
 365         info->cpu_freq = hw->get_cpu_freq(priv);
 366         info->features = BIT(CPU_FEAT_L1_CACHE);
 367         info->features |= BIT(CPU_FEAT_MMU);
 368         info->features |= BIT(CPU_FEAT_DEVICE_ID);
 369
 370         return 0;
 371 }
 372
 373 static int bmips_cpu_get_count(struct udevice *dev)
 374 {
 375         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 376         const struct bmips_cpu_hw *hw = priv->hw;
 377
 378         return hw->get_cpu_count(priv);
 379 }
 380
 381 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
 382 {
 383         snprintf(buf, size, "Broadcom");
 384
 385         return 0;
 386 }
 387
 388 static const struct cpu_ops bmips_cpu_ops = {
 389         .get_desc = bmips_cpu_get_desc,
 390         .get_info = bmips_cpu_get_info,
 391         .get_count = bmips_cpu_get_count,
 392         .get_vendor = bmips_cpu_get_vendor,
 393 };
 394
 395 /* BMIPS CPU driver */
 396 int bmips_cpu_bind(struct udevice *dev)
 397 {
 398         struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 399
 400         plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 401                 "reg", -1);
 402         plat->device_id = read_c0_prid();
 403
 404         return 0;
 405 }
 406
 407 int bmips_cpu_probe(struct udevice *dev)
 408 {
 409         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 410         const struct bmips_cpu_hw *hw =
 411                 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
 412         fdt_addr_t addr;
 413         fdt_size_t size;
 414
 415         addr = devfdt_get_addr_size_index(dev_get_parent(dev), 0, &size);
 416         if (addr == FDT_ADDR_T_NONE)
 417                 return -EINVAL;
 418
 419         priv->regs = ioremap(addr, size);
 420         priv->hw = hw;
 421
 422         return 0;
 423 }
 424
 425 static const struct udevice_id bmips_cpu_ids[] = {
 426         {
 427                 .compatible = "brcm,bcm3380-cpu",
 428                 .data = (ulong)&bmips_cpu_bcm3380,
 429         }, {
 430                 .compatible = "brcm,bcm6318-cpu",
 431                 .data = (ulong)&bmips_cpu_bcm6318,
 432         }, {
 433                 .compatible = "brcm,bcm6328-cpu",
 434                 .data = (ulong)&bmips_cpu_bcm6328,
 435         }, {
 436                 .compatible = "brcm,bcm6338-cpu",
 437                 .data = (ulong)&bmips_cpu_bcm6338,
 438         }, {
 439                 .compatible = "brcm,bcm6348-cpu",
 440                 .data = (ulong)&bmips_cpu_bcm6348,
 441         }, {
 442                 .compatible = "brcm,bcm6358-cpu",
 443                 .data = (ulong)&bmips_cpu_bcm6358,
 444         }, {
 445                 .compatible = "brcm,bcm6362-cpu",
 446                 .data = (ulong)&bmips_cpu_bcm6362,
 447         }, {
 448                 .compatible = "brcm,bcm6368-cpu",
 449                 .data = (ulong)&bmips_cpu_bcm6368,
 450         }, {
 451                 .compatible = "brcm,bcm63268-cpu",
 452                 .data = (ulong)&bmips_cpu_bcm63268,
 453         },
 454         { /* sentinel */ }
 455 };
 456
 457 U_BOOT_DRIVER(bmips_cpu_drv) = {
 458         .name = "bmips_cpu",
 459         .id = UCLASS_CPU,
 460         .of_match = bmips_cpu_ids,
 461         .bind = bmips_cpu_bind,
 462         .probe = bmips_cpu_probe,
 463         .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
 464         .ops = &bmips_cpu_ops,
 465         .flags = DM_FLAG_PRE_RELOC,
 466 };
 467
 468 #ifdef CONFIG_DISPLAY_CPUINFO
 469 int print_cpuinfo(void)
 470 {
 471         struct cpu_info cpu;
 472         struct udevice *dev;
 473         int err;
 474         char desc[100];
 475
 476         err = uclass_get_device(UCLASS_CPU, 0, &dev);
 477         if (err)
 478                 return 0;
 479
 480         err = cpu_get_info(dev, &cpu);
 481         if (err)
 482                 return 0;
 483
 484         err = cpu_get_desc(dev, desc, sizeof(desc));
 485         if (err)
 486                 return 0;
 487
 488         printf("Chip ID: %s, MIPS: ", desc);
 489         print_freq(cpu.cpu_freq, "\n");
 490
 491         return 0;
 492 }
 493 #endif