git.sur5r.net Git - u-boot/blob - drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #if !defined(CONFIG_SOC_KEYSTONE)
  38 #include <asm/gpio.h>
  39 #include <asm/arch/sys_proto.h>
  40 #endif
  41 #ifdef CONFIG_MMC_OMAP36XX_PINS
  42 #include <asm/arch/mux.h>
  43 #endif
  44 #include <dm.h>
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  49 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  50         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  51 #define OMAP_HSMMC_USE_GPIO
  52 #else
  53 #undef OMAP_HSMMC_USE_GPIO
  54 #endif
  55
  56 /* common definitions for all OMAPs */
  57 #define SYSCTL_SRC      (1 << 25)
  58 #define SYSCTL_SRD      (1 << 26)
  59
  60 struct omap_hsmmc_data {
  61         struct hsmmc *base_addr;
  62 #if !CONFIG_IS_ENABLED(DM_MMC)
  63         struct mmc_config cfg;
  64 #endif
  65         uint bus_width;
  66         uint clock;
  67 #ifdef OMAP_HSMMC_USE_GPIO
  68 #if CONFIG_IS_ENABLED(DM_MMC)
  69         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  70         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  71         bool cd_inverted;
  72 #else
  73         int cd_gpio;
  74         int wp_gpio;
  75 #endif
  76 #endif
  77 #if CONFIG_IS_ENABLED(DM_MMC)
  78         uint iov;
  79         enum bus_mode mode;
  80 #endif
  81         u8 controller_flags;
  82 #ifndef CONFIG_OMAP34XX
  83         struct omap_hsmmc_adma_desc *adma_desc_table;
  84         uint desc_slot;
  85 #endif
  86 };
  87
  88 #ifndef CONFIG_OMAP34XX
  89 struct omap_hsmmc_adma_desc {
  90         u8 attr;
  91         u8 reserved;
  92         u16 len;
  93         u32 addr;
  94 };
  95
  96 #define ADMA_MAX_LEN    63488
  97
  98 /* Decriptor table defines */
  99 #define ADMA_DESC_ATTR_VALID            BIT(0)
 100 #define ADMA_DESC_ATTR_END              BIT(1)
 101 #define ADMA_DESC_ATTR_INT              BIT(2)
 102 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 103 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 104
 105 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 106 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 107 #endif
 108
 109 /* If we fail after 1 second wait, something is really bad */
 110 #define MAX_RETRY_MS    1000
 111
 112 /* DMA transfers can take a long time if a lot a data is transferred.
 113  * The timeout must take in account the amount of data. Let's assume
 114  * that the time will never exceed 333 ms per MB (in other word we assume
 115  * that the bandwidth is always above 3MB/s).
 116  */
 117 #define DMA_TIMEOUT_PER_MB      333
 118 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 119 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 120 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 121
 122 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 123 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 124                         unsigned int siz);
 125 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 126 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 127
 128 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 129 {
 130 #if CONFIG_IS_ENABLED(DM_MMC)
 131         return dev_get_priv(mmc->dev);
 132 #else
 133         return (struct omap_hsmmc_data *)mmc->priv;
 134 #endif
 135 }
 136 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 137 {
 138 #if CONFIG_IS_ENABLED(DM_MMC)
 139         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 140         return &plat->cfg;
 141 #else
 142         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 143 #endif
 144 }
 145
 146 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 147 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 148 {
 149         int ret;
 150
 151 #ifndef CONFIG_DM_GPIO
 152         if (!gpio_is_valid(gpio))
 153                 return -1;
 154 #endif
 155         ret = gpio_request(gpio, label);
 156         if (ret)
 157                 return ret;
 158
 159         ret = gpio_direction_input(gpio);
 160         if (ret)
 161                 return ret;
 162
 163         return gpio;
 164 }
 165 #endif
 166
 167 static unsigned char mmc_board_init(struct mmc *mmc)
 168 {
 169 #if defined(CONFIG_OMAP34XX)
 170         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 171         t2_t *t2_base = (t2_t *)T2_BASE;
 172         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 173         u32 pbias_lite;
 174 #ifdef CONFIG_MMC_OMAP36XX_PINS
 175         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 176 #endif
 177
 178         pbias_lite = readl(&t2_base->pbias_lite);
 179         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 180 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 181         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 182         pbias_lite &= ~PBIASLITEVMODE0;
 183 #endif
 184 #ifdef CONFIG_MMC_OMAP36XX_PINS
 185         if (get_cpu_family() == CPU_OMAP36XX) {
 186                 /* Disable extended drain IO before changing PBIAS */
 187                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 188                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 189         }
 190 #endif
 191         writel(pbias_lite, &t2_base->pbias_lite);
 192
 193         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 194                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 195                 &t2_base->pbias_lite);
 196
 197 #ifdef CONFIG_MMC_OMAP36XX_PINS
 198         if (get_cpu_family() == CPU_OMAP36XX)
 199                 /* Enable extended drain IO after changing PBIAS */
 200                 writel(wkup_ctrl |
 201                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 202                                 OMAP34XX_CTRL_WKUP_CTRL);
 203 #endif
 204         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 205                 &t2_base->devconf0);
 206
 207         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 208                 &t2_base->devconf1);
 209
 210         /* Change from default of 52MHz to 26MHz if necessary */
 211         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 212                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 213                         &t2_base->ctl_prog_io1);
 214
 215         writel(readl(&prcm_base->fclken1_core) |
 216                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 217                 &prcm_base->fclken1_core);
 218
 219         writel(readl(&prcm_base->iclken1_core) |
 220                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 221                 &prcm_base->iclken1_core);
 222 #endif
 223
 224 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 225         /* PBIAS config needed for MMC1 only */
 226         if (mmc_get_blk_desc(mmc)->devnum == 0)
 227                 vmmc_pbias_config(LDO_VOLT_3V0);
 228 #endif
 229
 230         return 0;
 231 }
 232
 233 void mmc_init_stream(struct hsmmc *mmc_base)
 234 {
 235         ulong start;
 236
 237         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 238
 239         writel(MMC_CMD0, &mmc_base->cmd);
 240         start = get_timer(0);
 241         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 242                 if (get_timer(0) - start > MAX_RETRY_MS) {
 243                         printf("%s: timedout waiting for cc!\n", __func__);
 244                         return;
 245                 }
 246         }
 247         writel(CC_MASK, &mmc_base->stat)
 248                 ;
 249         writel(MMC_CMD0, &mmc_base->cmd)
 250                 ;
 251         start = get_timer(0);
 252         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 253                 if (get_timer(0) - start > MAX_RETRY_MS) {
 254                         printf("%s: timedout waiting for cc2!\n", __func__);
 255                         return;
 256                 }
 257         }
 258         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 259 }
 260
 261 #if CONFIG_IS_ENABLED(DM_MMC)
 262 static void omap_hsmmc_set_timing(struct mmc *mmc)
 263 {
 264         u32 val;
 265         struct hsmmc *mmc_base;
 266         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 267
 268         mmc_base = priv->base_addr;
 269
 270         val = readl(&mmc_base->ac12);
 271         val &= ~AC12_UHSMC_MASK;
 272         priv->mode = mmc->selected_mode;
 273
 274         if (mmc_is_mode_ddr(priv->mode))
 275                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 276         else
 277                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 278
 279         switch (priv->mode) {
 280         case MMC_HS_200:
 281         case UHS_SDR104:
 282                 val |= AC12_UHSMC_SDR104;
 283                 break;
 284         case UHS_SDR50:
 285                 val |= AC12_UHSMC_SDR50;
 286                 break;
 287         case MMC_DDR_52:
 288         case UHS_DDR50:
 289                 val |= AC12_UHSMC_DDR50;
 290                 break;
 291         case SD_HS:
 292         case MMC_HS_52:
 293         case UHS_SDR25:
 294                 val |= AC12_UHSMC_SDR25;
 295                 break;
 296         case MMC_LEGACY:
 297         case MMC_HS:
 298         case SD_LEGACY:
 299         case UHS_SDR12:
 300                 val |= AC12_UHSMC_SDR12;
 301                 break;
 302         default:
 303                 val |= AC12_UHSMC_RES;
 304                 break;
 305         }
 306         writel(val, &mmc_base->ac12);
 307 }
 308
 309 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
 310 {
 311         struct hsmmc *mmc_base;
 312         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 313         u32 val;
 314
 315         mmc_base = priv->base_addr;
 316
 317         val = readl(&mmc_base->hctl) & ~SDVS_MASK;
 318
 319         switch (priv->iov) {
 320         case IOV_3V3:
 321                 val |= SDVS_3V3;
 322                 break;
 323         case IOV_3V0:
 324                 val |= SDVS_3V0;
 325                 break;
 326         case IOV_1V8:
 327                 val |= SDVS_1V8;
 328                 break;
 329         }
 330
 331         writel(val, &mmc_base->hctl);
 332 }
 333
 334 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 335 {
 336         struct hsmmc *mmc_base;
 337         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 338         u32 val;
 339
 340         mmc_base = priv->base_addr;
 341         val = readl(&mmc_base->capa);
 342
 343         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 344                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 345                 priv->iov = IOV_3V0;
 346         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 347                 val |= VS30_3V0SUP;
 348                 val &= ~VS18_1V8SUP;
 349                 priv->iov = IOV_3V0;
 350         } else {
 351                 val |= VS18_1V8SUP;
 352                 val &= ~VS30_3V0SUP;
 353                 priv->iov = IOV_1V8;
 354         }
 355
 356         writel(val, &mmc_base->capa);
 357 }
 358 #endif
 359
 360 static int omap_hsmmc_init_setup(struct mmc *mmc)
 361 {
 362         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 363         struct hsmmc *mmc_base;
 364         unsigned int reg_val;
 365         unsigned int dsor;
 366         ulong start;
 367
 368         mmc_base = priv->base_addr;
 369         mmc_board_init(mmc);
 370
 371         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 372                 &mmc_base->sysconfig);
 373         start = get_timer(0);
 374         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 375                 if (get_timer(0) - start > MAX_RETRY_MS) {
 376                         printf("%s: timedout waiting for cc2!\n", __func__);
 377                         return -ETIMEDOUT;
 378                 }
 379         }
 380         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 381         start = get_timer(0);
 382         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 383                 if (get_timer(0) - start > MAX_RETRY_MS) {
 384                         printf("%s: timedout waiting for softresetall!\n",
 385                                 __func__);
 386                         return -ETIMEDOUT;
 387                 }
 388         }
 389 #ifndef CONFIG_OMAP34XX
 390         reg_val = readl(&mmc_base->hl_hwinfo);
 391         if (reg_val & MADMA_EN)
 392                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 393 #endif
 394
 395 #if CONFIG_IS_ENABLED(DM_MMC)
 396         omap_hsmmc_set_capabilities(mmc);
 397         omap_hsmmc_conf_bus_power(mmc);
 398 #else
 399         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 400         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 401                 &mmc_base->capa);
 402 #endif
 403
 404         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 405
 406         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 407                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 408                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 409
 410         dsor = 240;
 411         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 412                 (ICE_STOP | DTO_15THDTO));
 413         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 414                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 415         start = get_timer(0);
 416         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 417                 if (get_timer(0) - start > MAX_RETRY_MS) {
 418                         printf("%s: timedout waiting for ics!\n", __func__);
 419                         return -ETIMEDOUT;
 420                 }
 421         }
 422         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 423
 424         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 425
 426         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 427                 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
 428                 IE_CC, &mmc_base->ie);
 429
 430         mmc_init_stream(mmc_base);
 431
 432         return 0;
 433 }
 434
 435 /*
 436  * MMC controller internal finite state machine reset
 437  *
 438  * Used to reset command or data internal state machines, using respectively
 439  * SRC or SRD bit of SYSCTL register
 440  */
 441 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 442 {
 443         ulong start;
 444
 445         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 446
 447         /*
 448          * CMD(DAT) lines reset procedures are slightly different
 449          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 450          * According to OMAP3 TRM:
 451          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 452          * returns to 0x0.
 453          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 454          * procedure steps must be as follows:
 455          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 456          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 457          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 458          * 3. Wait until the SRC (SRD) bit returns to 0x0
 459          *    (reset procedure is completed).
 460          */
 461 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 462         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 463         if (!(readl(&mmc_base->sysctl) & bit)) {
 464                 start = get_timer(0);
 465                 while (!(readl(&mmc_base->sysctl) & bit)) {
 466                         if (get_timer(0) - start > MAX_RETRY_MS)
 467                                 return;
 468                 }
 469         }
 470 #endif
 471         start = get_timer(0);
 472         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 473                 if (get_timer(0) - start > MAX_RETRY_MS) {
 474                         printf("%s: timedout waiting for sysctl %x to clear\n",
 475                                 __func__, bit);
 476                         return;
 477                 }
 478         }
 479 }
 480
 481 #ifndef CONFIG_OMAP34XX
 482 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 483 {
 484         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 485         struct omap_hsmmc_adma_desc *desc;
 486         u8 attr;
 487
 488         desc = &priv->adma_desc_table[priv->desc_slot];
 489
 490         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 491         if (!end)
 492                 priv->desc_slot++;
 493         else
 494                 attr |= ADMA_DESC_ATTR_END;
 495
 496         desc->len = len;
 497         desc->addr = (u32)buf;
 498         desc->reserved = 0;
 499         desc->attr = attr;
 500 }
 501
 502 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 503                                           struct mmc_data *data)
 504 {
 505         uint total_len = data->blocksize * data->blocks;
 506         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 507         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 508         int i = desc_count;
 509         char *buf;
 510
 511         priv->desc_slot = 0;
 512         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 513                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 514                                 sizeof(struct omap_hsmmc_adma_desc));
 515
 516         if (data->flags & MMC_DATA_READ)
 517                 buf = data->dest;
 518         else
 519                 buf = (char *)data->src;
 520
 521         while (--i) {
 522                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 523                 buf += ADMA_MAX_LEN;
 524                 total_len -= ADMA_MAX_LEN;
 525         }
 526
 527         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 528
 529         flush_dcache_range((long)priv->adma_desc_table,
 530                            (long)priv->adma_desc_table +
 531                            ROUND(desc_count *
 532                            sizeof(struct omap_hsmmc_adma_desc),
 533                            ARCH_DMA_MINALIGN));
 534 }
 535
 536 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 537 {
 538         struct hsmmc *mmc_base;
 539         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 540         u32 val;
 541         char *buf;
 542
 543         mmc_base = priv->base_addr;
 544         omap_hsmmc_prepare_adma_table(mmc, data);
 545
 546         if (data->flags & MMC_DATA_READ)
 547                 buf = data->dest;
 548         else
 549                 buf = (char *)data->src;
 550
 551         val = readl(&mmc_base->hctl);
 552         val |= DMA_SELECT;
 553         writel(val, &mmc_base->hctl);
 554
 555         val = readl(&mmc_base->con);
 556         val |= DMA_MASTER;
 557         writel(val, &mmc_base->con);
 558
 559         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 560
 561         flush_dcache_range((u32)buf,
 562                            (u32)buf +
 563                            ROUND(data->blocksize * data->blocks,
 564                                  ARCH_DMA_MINALIGN));
 565 }
 566
 567 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
 568 {
 569         struct hsmmc *mmc_base;
 570         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 571         u32 val;
 572
 573         mmc_base = priv->base_addr;
 574
 575         val = readl(&mmc_base->con);
 576         val &= ~DMA_MASTER;
 577         writel(val, &mmc_base->con);
 578
 579         val = readl(&mmc_base->hctl);
 580         val &= ~DMA_SELECT;
 581         writel(val, &mmc_base->hctl);
 582
 583         kfree(priv->adma_desc_table);
 584 }
 585 #else
 586 #define omap_hsmmc_adma_desc
 587 #define omap_hsmmc_prepare_adma_table
 588 #define omap_hsmmc_prepare_data
 589 #define omap_hsmmc_dma_cleanup
 590 #endif
 591
 592 #if !CONFIG_IS_ENABLED(DM_MMC)
 593 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 594                         struct mmc_data *data)
 595 {
 596         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 597 #else
 598 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 599                         struct mmc_data *data)
 600 {
 601         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 602 #ifndef CONFIG_OMAP34XX
 603         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 604         struct mmc *mmc = upriv->mmc;
 605 #endif
 606 #endif
 607         struct hsmmc *mmc_base;
 608         unsigned int flags, mmc_stat;
 609         ulong start;
 610
 611         mmc_base = priv->base_addr;
 612
 613         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 614                 return 0;
 615
 616         start = get_timer(0);
 617         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 618                 if (get_timer(0) - start > MAX_RETRY_MS) {
 619                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 620                                         __func__);
 621                         return -ETIMEDOUT;
 622                 }
 623         }
 624         writel(0xFFFFFFFF, &mmc_base->stat);
 625         start = get_timer(0);
 626         while (readl(&mmc_base->stat)) {
 627                 if (get_timer(0) - start > MAX_RETRY_MS) {
 628                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 629                                 __func__, readl(&mmc_base->stat));
 630                         return -ETIMEDOUT;
 631                 }
 632         }
 633         /*
 634          * CMDREG
 635          * CMDIDX[13:8] : Command index
 636          * DATAPRNT[5]  : Data Present Select
 637          * ENCMDIDX[4]  : Command Index Check Enable
 638          * ENCMDCRC[3]  : Command CRC Check Enable
 639          * RSPTYP[1:0]
 640          *      00 = No Response
 641          *      01 = Length 136
 642          *      10 = Length 48
 643          *      11 = Length 48 Check busy after response
 644          */
 645         /* Delay added before checking the status of frq change
 646          * retry not supported by mmc.c(core file)
 647          */
 648         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 649                 udelay(50000); /* wait 50 ms */
 650
 651         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 652                 flags = 0;
 653         else if (cmd->resp_type & MMC_RSP_136)
 654                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 655         else if (cmd->resp_type & MMC_RSP_BUSY)
 656                 flags = RSP_TYPE_LGHT48B;
 657         else
 658                 flags = RSP_TYPE_LGHT48;
 659
 660         /* enable default flags */
 661         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 662                         MSBS_SGLEBLK);
 663         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 664
 665         if (cmd->resp_type & MMC_RSP_CRC)
 666                 flags |= CCCE_CHECK;
 667         if (cmd->resp_type & MMC_RSP_OPCODE)
 668                 flags |= CICE_CHECK;
 669
 670         if (data) {
 671                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 672                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 673                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
 674                         data->blocksize = 512;
 675                         writel(data->blocksize | (data->blocks << 16),
 676                                                         &mmc_base->blk);
 677                 } else
 678                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 679
 680                 if (data->flags & MMC_DATA_READ)
 681                         flags |= (DP_DATA | DDIR_READ);
 682                 else
 683                         flags |= (DP_DATA | DDIR_WRITE);
 684
 685 #ifndef CONFIG_OMAP34XX
 686                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
 687                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
 688                         omap_hsmmc_prepare_data(mmc, data);
 689                         flags |= DE_ENABLE;
 690                 }
 691 #endif
 692         }
 693
 694         writel(cmd->cmdarg, &mmc_base->arg);
 695         udelay(20);             /* To fix "No status update" error on eMMC */
 696         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 697
 698         start = get_timer(0);
 699         do {
 700                 mmc_stat = readl(&mmc_base->stat);
 701                 if (get_timer(start) > MAX_RETRY_MS) {
 702                         printf("%s : timeout: No status update\n", __func__);
 703                         return -ETIMEDOUT;
 704                 }
 705         } while (!mmc_stat);
 706
 707         if ((mmc_stat & IE_CTO) != 0) {
 708                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 709                 return -ETIMEDOUT;
 710         } else if ((mmc_stat & ERRI_MASK) != 0)
 711                 return -1;
 712
 713         if (mmc_stat & CC_MASK) {
 714                 writel(CC_MASK, &mmc_base->stat);
 715                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 716                         if (cmd->resp_type & MMC_RSP_136) {
 717                                 /* response type 2 */
 718                                 cmd->response[3] = readl(&mmc_base->rsp10);
 719                                 cmd->response[2] = readl(&mmc_base->rsp32);
 720                                 cmd->response[1] = readl(&mmc_base->rsp54);
 721                                 cmd->response[0] = readl(&mmc_base->rsp76);
 722                         } else
 723                                 /* response types 1, 1b, 3, 4, 5, 6 */
 724                                 cmd->response[0] = readl(&mmc_base->rsp10);
 725                 }
 726         }
 727
 728 #ifndef CONFIG_OMAP34XX
 729         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
 730             !mmc_is_tuning_cmd(cmd->cmdidx)) {
 731                 u32 sz_mb, timeout;
 732
 733                 if (mmc_stat & IE_ADMAE) {
 734                         omap_hsmmc_dma_cleanup(mmc);
 735                         return -EIO;
 736                 }
 737
 738                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
 739                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
 740                 if (timeout < MAX_RETRY_MS)
 741                         timeout = MAX_RETRY_MS;
 742
 743                 start = get_timer(0);
 744                 do {
 745                         mmc_stat = readl(&mmc_base->stat);
 746                         if (mmc_stat & TC_MASK) {
 747                                 writel(readl(&mmc_base->stat) | TC_MASK,
 748                                        &mmc_base->stat);
 749                                 break;
 750                         }
 751                         if (get_timer(start) > timeout) {
 752                                 printf("%s : DMA timeout: No status update\n",
 753                                        __func__);
 754                                 return -ETIMEDOUT;
 755                         }
 756                 } while (1);
 757
 758                 omap_hsmmc_dma_cleanup(mmc);
 759                 return 0;
 760         }
 761 #endif
 762
 763         if (data && (data->flags & MMC_DATA_READ)) {
 764                 mmc_read_data(mmc_base, data->dest,
 765                                 data->blocksize * data->blocks);
 766         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 767                 mmc_write_data(mmc_base, data->src,
 768                                 data->blocksize * data->blocks);
 769         }
 770         return 0;
 771 }
 772
 773 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 774 {
 775         unsigned int *output_buf = (unsigned int *)buf;
 776         unsigned int mmc_stat;
 777         unsigned int count;
 778
 779         /*
 780          * Start Polled Read
 781          */
 782         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 783         count /= 4;
 784
 785         while (size) {
 786                 ulong start = get_timer(0);
 787                 do {
 788                         mmc_stat = readl(&mmc_base->stat);
 789                         if (get_timer(0) - start > MAX_RETRY_MS) {
 790                                 printf("%s: timedout waiting for status!\n",
 791                                                 __func__);
 792                                 return -ETIMEDOUT;
 793                         }
 794                 } while (mmc_stat == 0);
 795
 796                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 797                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 798
 799                 if ((mmc_stat & ERRI_MASK) != 0)
 800                         return 1;
 801
 802                 if (mmc_stat & BRR_MASK) {
 803                         unsigned int k;
 804
 805                         writel(readl(&mmc_base->stat) | BRR_MASK,
 806                                 &mmc_base->stat);
 807                         for (k = 0; k < count; k++) {
 808                                 *output_buf = readl(&mmc_base->data);
 809                                 output_buf++;
 810                         }
 811                         size -= (count*4);
 812                 }
 813
 814                 if (mmc_stat & BWR_MASK)
 815                         writel(readl(&mmc_base->stat) | BWR_MASK,
 816                                 &mmc_base->stat);
 817
 818                 if (mmc_stat & TC_MASK) {
 819                         writel(readl(&mmc_base->stat) | TC_MASK,
 820                                 &mmc_base->stat);
 821                         break;
 822                 }
 823         }
 824         return 0;
 825 }
 826
 827 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 828                                 unsigned int size)
 829 {
 830         unsigned int *input_buf = (unsigned int *)buf;
 831         unsigned int mmc_stat;
 832         unsigned int count;
 833
 834         /*
 835          * Start Polled Write
 836          */
 837         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 838         count /= 4;
 839
 840         while (size) {
 841                 ulong start = get_timer(0);
 842                 do {
 843                         mmc_stat = readl(&mmc_base->stat);
 844                         if (get_timer(0) - start > MAX_RETRY_MS) {
 845                                 printf("%s: timedout waiting for status!\n",
 846                                                 __func__);
 847                                 return -ETIMEDOUT;
 848                         }
 849                 } while (mmc_stat == 0);
 850
 851                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 852                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 853
 854                 if ((mmc_stat & ERRI_MASK) != 0)
 855                         return 1;
 856
 857                 if (mmc_stat & BWR_MASK) {
 858                         unsigned int k;
 859
 860                         writel(readl(&mmc_base->stat) | BWR_MASK,
 861                                         &mmc_base->stat);
 862                         for (k = 0; k < count; k++) {
 863                                 writel(*input_buf, &mmc_base->data);
 864                                 input_buf++;
 865                         }
 866                         size -= (count*4);
 867                 }
 868
 869                 if (mmc_stat & BRR_MASK)
 870                         writel(readl(&mmc_base->stat) | BRR_MASK,
 871                                 &mmc_base->stat);
 872
 873                 if (mmc_stat & TC_MASK) {
 874                         writel(readl(&mmc_base->stat) | TC_MASK,
 875                                 &mmc_base->stat);
 876                         break;
 877                 }
 878         }
 879         return 0;
 880 }
 881
 882 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
 883 {
 884         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
 885 }
 886
 887 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
 888 {
 889         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 890 }
 891
 892 static void omap_hsmmc_set_clock(struct mmc *mmc)
 893 {
 894         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 895         struct hsmmc *mmc_base;
 896         unsigned int dsor = 0;
 897         ulong start;
 898
 899         mmc_base = priv->base_addr;
 900         omap_hsmmc_stop_clock(mmc_base);
 901
 902         /* TODO: Is setting DTO required here? */
 903         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
 904                     (ICE_STOP | DTO_15THDTO));
 905
 906         if (mmc->clock != 0) {
 907                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
 908                 if (dsor > CLKD_MAX)
 909                         dsor = CLKD_MAX;
 910         } else {
 911                 dsor = CLKD_MAX;
 912         }
 913
 914         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 915                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 916
 917         start = get_timer(0);
 918         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 919                 if (get_timer(0) - start > MAX_RETRY_MS) {
 920                         printf("%s: timedout waiting for ics!\n", __func__);
 921                         return;
 922                 }
 923         }
 924
 925         priv->clock = mmc->clock;
 926         omap_hsmmc_start_clock(mmc_base);
 927 }
 928
 929 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
 930 {
 931         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 932         struct hsmmc *mmc_base;
 933
 934         mmc_base = priv->base_addr;
 935         /* configue bus width */
 936         switch (mmc->bus_width) {
 937         case 8:
 938                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 939                         &mmc_base->con);
 940                 break;
 941
 942         case 4:
 943                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 944                         &mmc_base->con);
 945                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 946                         &mmc_base->hctl);
 947                 break;
 948
 949         case 1:
 950         default:
 951                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 952                         &mmc_base->con);
 953                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 954                         &mmc_base->hctl);
 955                 break;
 956         }
 957
 958         priv->bus_width = mmc->bus_width;
 959 }
 960
 961 #if !CONFIG_IS_ENABLED(DM_MMC)
 962 static int omap_hsmmc_set_ios(struct mmc *mmc)
 963 {
 964         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 965 #else
 966 static int omap_hsmmc_set_ios(struct udevice *dev)
 967 {
 968         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 969         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 970         struct mmc *mmc = upriv->mmc;
 971 #endif
 972
 973         if (priv->bus_width != mmc->bus_width)
 974                 omap_hsmmc_set_bus_width(mmc);
 975
 976         if (priv->clock != mmc->clock)
 977                 omap_hsmmc_set_clock(mmc);
 978
 979 #if CONFIG_IS_ENABLED(DM_MMC)
 980         if (priv->mode != mmc->selected_mode)
 981                 omap_hsmmc_set_timing(mmc);
 982 #endif
 983         return 0;
 984 }
 985
 986 #ifdef OMAP_HSMMC_USE_GPIO
 987 #if CONFIG_IS_ENABLED(DM_MMC)
 988 static int omap_hsmmc_getcd(struct udevice *dev)
 989 {
 990         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 991         int value;
 992
 993         value = dm_gpio_get_value(&priv->cd_gpio);
 994         /* if no CD return as 1 */
 995         if (value < 0)
 996                 return 1;
 997
 998         if (priv->cd_inverted)
 999                 return !value;
1000         return value;
1001 }
1002
1003 static int omap_hsmmc_getwp(struct udevice *dev)
1004 {
1005         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1006         int value;
1007
1008         value = dm_gpio_get_value(&priv->wp_gpio);
1009         /* if no WP return as 0 */
1010         if (value < 0)
1011                 return 0;
1012         return value;
1013 }
1014 #else
1015 static int omap_hsmmc_getcd(struct mmc *mmc)
1016 {
1017         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1018         int cd_gpio;
1019
1020         /* if no CD return as 1 */
1021         cd_gpio = priv->cd_gpio;
1022         if (cd_gpio < 0)
1023                 return 1;
1024
1025         /* NOTE: assumes card detect signal is active-low */
1026         return !gpio_get_value(cd_gpio);
1027 }
1028
1029 static int omap_hsmmc_getwp(struct mmc *mmc)
1030 {
1031         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1032         int wp_gpio;
1033
1034         /* if no WP return as 0 */
1035         wp_gpio = priv->wp_gpio;
1036         if (wp_gpio < 0)
1037                 return 0;
1038
1039         /* NOTE: assumes write protect signal is active-high */
1040         return gpio_get_value(wp_gpio);
1041 }
1042 #endif
1043 #endif
1044
1045 #if CONFIG_IS_ENABLED(DM_MMC)
1046 static const struct dm_mmc_ops omap_hsmmc_ops = {
1047         .send_cmd       = omap_hsmmc_send_cmd,
1048         .set_ios        = omap_hsmmc_set_ios,
1049 #ifdef OMAP_HSMMC_USE_GPIO
1050         .get_cd         = omap_hsmmc_getcd,
1051         .get_wp         = omap_hsmmc_getwp,
1052 #endif
1053 };
1054 #else
1055 static const struct mmc_ops omap_hsmmc_ops = {
1056         .send_cmd       = omap_hsmmc_send_cmd,
1057         .set_ios        = omap_hsmmc_set_ios,
1058         .init           = omap_hsmmc_init_setup,
1059 #ifdef OMAP_HSMMC_USE_GPIO
1060         .getcd          = omap_hsmmc_getcd,
1061         .getwp          = omap_hsmmc_getwp,
1062 #endif
1063 };
1064 #endif
1065
1066 #if !CONFIG_IS_ENABLED(DM_MMC)
1067 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1068                 int wp_gpio)
1069 {
1070         struct mmc *mmc;
1071         struct omap_hsmmc_data *priv;
1072         struct mmc_config *cfg;
1073         uint host_caps_val;
1074
1075         priv = malloc(sizeof(*priv));
1076         if (priv == NULL)
1077                 return -1;
1078
1079         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1080
1081         switch (dev_index) {
1082         case 0:
1083                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1084                 break;
1085 #ifdef OMAP_HSMMC2_BASE
1086         case 1:
1087                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1088 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1089         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1090         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1091                 defined(CONFIG_HSMMC2_8BIT)
1092                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1093                 host_caps_val |= MMC_MODE_8BIT;
1094 #endif
1095                 break;
1096 #endif
1097 #ifdef OMAP_HSMMC3_BASE
1098         case 2:
1099                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1100 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1101                 /* Enable 8-bit interface for eMMC on DRA7XX */
1102                 host_caps_val |= MMC_MODE_8BIT;
1103 #endif
1104                 break;
1105 #endif
1106         default:
1107                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1108                 return 1;
1109         }
1110 #ifdef OMAP_HSMMC_USE_GPIO
1111         /* on error gpio values are set to -1, which is what we want */
1112         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1113         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1114 #endif
1115
1116         cfg = &priv->cfg;
1117
1118         cfg->name = "OMAP SD/MMC";
1119         cfg->ops = &omap_hsmmc_ops;
1120
1121         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1122         cfg->host_caps = host_caps_val & ~host_caps_mask;
1123
1124         cfg->f_min = 400000;
1125
1126         if (f_max != 0)
1127                 cfg->f_max = f_max;
1128         else {
1129                 if (cfg->host_caps & MMC_MODE_HS) {
1130                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1131                                 cfg->f_max = 52000000;
1132                         else
1133                                 cfg->f_max = 26000000;
1134                 } else
1135                         cfg->f_max = 20000000;
1136         }
1137
1138         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1139
1140 #if defined(CONFIG_OMAP34XX)
1141         /*
1142          * Silicon revs 2.1 and older do not support multiblock transfers.
1143          */
1144         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1145                 cfg->b_max = 1;
1146 #endif
1147         mmc = mmc_create(cfg, priv);
1148         if (mmc == NULL)
1149                 return -1;
1150
1151         return 0;
1152 }
1153 #else
1154 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1155 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1156 {
1157         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1158         struct mmc_config *cfg = &plat->cfg;
1159         const void *fdt = gd->fdt_blob;
1160         int node = dev_of_offset(dev);
1161         int val;
1162
1163         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1164                                       sizeof(struct hsmmc *),
1165                                       MAP_NOCACHE);
1166
1167         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1168         val = fdtdec_get_int(fdt, node, "bus-width", -1);
1169         if (val < 0) {
1170                 printf("error: bus-width property missing\n");
1171                 return -ENOENT;
1172         }
1173
1174         switch (val) {
1175         case 0x8:
1176                 cfg->host_caps |= MMC_MODE_8BIT;
1177         case 0x4:
1178                 cfg->host_caps |= MMC_MODE_4BIT;
1179                 break;
1180         default:
1181                 printf("error: invalid bus-width property\n");
1182                 return -ENOENT;
1183         }
1184
1185         cfg->f_min = 400000;
1186         cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1187         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1188         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1189         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1190                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1191         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1192                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1193
1194 #ifdef OMAP_HSMMC_USE_GPIO
1195         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1196 #endif
1197
1198         return 0;
1199 }
1200 #endif
1201
1202 #ifdef CONFIG_BLK
1203
1204 static int omap_hsmmc_bind(struct udevice *dev)
1205 {
1206         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1207
1208         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1209 }
1210 #endif
1211 static int omap_hsmmc_probe(struct udevice *dev)
1212 {
1213         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1214         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1215         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1216         struct mmc_config *cfg = &plat->cfg;
1217         struct mmc *mmc;
1218
1219         cfg->name = "OMAP SD/MMC";
1220         priv->base_addr = plat->base_addr;
1221 #ifdef OMAP_HSMMC_USE_GPIO
1222         priv->cd_inverted = plat->cd_inverted;
1223 #endif
1224
1225 #ifdef CONFIG_BLK
1226         mmc = &plat->mmc;
1227 #else
1228         mmc = mmc_create(cfg, priv);
1229         if (mmc == NULL)
1230                 return -1;
1231 #endif
1232
1233 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1234         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1235         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1236 #endif
1237
1238         mmc->dev = dev;
1239         upriv->mmc = mmc;
1240
1241         return omap_hsmmc_init_setup(mmc);
1242 }
1243
1244 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1245 static const struct udevice_id omap_hsmmc_ids[] = {
1246         { .compatible = "ti,omap3-hsmmc" },
1247         { .compatible = "ti,omap4-hsmmc" },
1248         { .compatible = "ti,am33xx-hsmmc" },
1249         { }
1250 };
1251 #endif
1252
1253 U_BOOT_DRIVER(omap_hsmmc) = {
1254         .name   = "omap_hsmmc",
1255         .id     = UCLASS_MMC,
1256 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1257         .of_match = omap_hsmmc_ids,
1258         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1259         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1260 #endif
1261 #ifdef CONFIG_BLK
1262         .bind = omap_hsmmc_bind,
1263 #endif
1264         .ops = &omap_hsmmc_ops,
1265         .probe  = omap_hsmmc_probe,
1266         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1267         .flags  = DM_FLAG_PRE_RELOC,
1268 };
1269 #endif