git.sur5r.net Git - u-boot/blob - drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  53 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  54         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  55 #define OMAP_HSMMC_USE_GPIO
  56 #else
  57 #undef OMAP_HSMMC_USE_GPIO
  58 #endif
  59
  60 /* common definitions for all OMAPs */
  61 #define SYSCTL_SRC      (1 << 25)
  62 #define SYSCTL_SRD      (1 << 26)
  63
  64 #ifdef CONFIG_IODELAY_RECALIBRATION
  65 struct omap_hsmmc_pinctrl_state {
  66         struct pad_conf_entry *padconf;
  67         int npads;
  68         struct iodelay_cfg_entry *iodelay;
  69         int niodelays;
  70 };
  71 #endif
  72
  73 struct omap_hsmmc_data {
  74         struct hsmmc *base_addr;
  75 #if !CONFIG_IS_ENABLED(DM_MMC)
  76         struct mmc_config cfg;
  77 #endif
  78         uint bus_width;
  79         uint clock;
  80 #ifdef OMAP_HSMMC_USE_GPIO
  81 #if CONFIG_IS_ENABLED(DM_MMC)
  82         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  83         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  84         bool cd_inverted;
  85 #else
  86         int cd_gpio;
  87         int wp_gpio;
  88 #endif
  89 #endif
  90 #if CONFIG_IS_ENABLED(DM_MMC)
  91         uint iov;
  92         enum bus_mode mode;
  93 #endif
  94         u8 controller_flags;
  95 #ifndef CONFIG_OMAP34XX
  96         struct omap_hsmmc_adma_desc *adma_desc_table;
  97         uint desc_slot;
  98 #endif
  99         const char *hw_rev;
 100 #ifdef CONFIG_IODELAY_RECALIBRATION
 101         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 102         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 103         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 104         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 110 #endif
 111 };
 112
 113 struct omap_mmc_of_data {
 114         u8 controller_flags;
 115 };
 116
 117 #ifndef CONFIG_OMAP34XX
 118 struct omap_hsmmc_adma_desc {
 119         u8 attr;
 120         u8 reserved;
 121         u16 len;
 122         u32 addr;
 123 };
 124
 125 #define ADMA_MAX_LEN    63488
 126
 127 /* Decriptor table defines */
 128 #define ADMA_DESC_ATTR_VALID            BIT(0)
 129 #define ADMA_DESC_ATTR_END              BIT(1)
 130 #define ADMA_DESC_ATTR_INT              BIT(2)
 131 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 132 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 133
 134 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 135 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 136 #endif
 137
 138 /* If we fail after 1 second wait, something is really bad */
 139 #define MAX_RETRY_MS    1000
 140 #define MMC_TIMEOUT_MS  20
 141
 142 /* DMA transfers can take a long time if a lot a data is transferred.
 143  * The timeout must take in account the amount of data. Let's assume
 144  * that the time will never exceed 333 ms per MB (in other word we assume
 145  * that the bandwidth is always above 3MB/s).
 146  */
 147 #define DMA_TIMEOUT_PER_MB      333
 148 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 149 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 150 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 151 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 152
 153 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 154 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 155                         unsigned int siz);
 156 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 157 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 158 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 159
 160 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 161 {
 162 #if CONFIG_IS_ENABLED(DM_MMC)
 163         return dev_get_priv(mmc->dev);
 164 #else
 165         return (struct omap_hsmmc_data *)mmc->priv;
 166 #endif
 167 }
 168 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 169 {
 170 #if CONFIG_IS_ENABLED(DM_MMC)
 171         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 172         return &plat->cfg;
 173 #else
 174         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 175 #endif
 176 }
 177
 178 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 179 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 180 {
 181         int ret;
 182
 183 #ifndef CONFIG_DM_GPIO
 184         if (!gpio_is_valid(gpio))
 185                 return -1;
 186 #endif
 187         ret = gpio_request(gpio, label);
 188         if (ret)
 189                 return ret;
 190
 191         ret = gpio_direction_input(gpio);
 192         if (ret)
 193                 return ret;
 194
 195         return gpio;
 196 }
 197 #endif
 198
 199 static unsigned char mmc_board_init(struct mmc *mmc)
 200 {
 201 #if defined(CONFIG_OMAP34XX)
 202         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 203         t2_t *t2_base = (t2_t *)T2_BASE;
 204         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 205         u32 pbias_lite;
 206 #ifdef CONFIG_MMC_OMAP36XX_PINS
 207         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 208 #endif
 209
 210         pbias_lite = readl(&t2_base->pbias_lite);
 211         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 212 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 213         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 214         pbias_lite &= ~PBIASLITEVMODE0;
 215 #endif
 216 #ifdef CONFIG_MMC_OMAP36XX_PINS
 217         if (get_cpu_family() == CPU_OMAP36XX) {
 218                 /* Disable extended drain IO before changing PBIAS */
 219                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 220                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 221         }
 222 #endif
 223         writel(pbias_lite, &t2_base->pbias_lite);
 224
 225         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 226                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 227                 &t2_base->pbias_lite);
 228
 229 #ifdef CONFIG_MMC_OMAP36XX_PINS
 230         if (get_cpu_family() == CPU_OMAP36XX)
 231                 /* Enable extended drain IO after changing PBIAS */
 232                 writel(wkup_ctrl |
 233                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 234                                 OMAP34XX_CTRL_WKUP_CTRL);
 235 #endif
 236         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 237                 &t2_base->devconf0);
 238
 239         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 240                 &t2_base->devconf1);
 241
 242         /* Change from default of 52MHz to 26MHz if necessary */
 243         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 244                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 245                         &t2_base->ctl_prog_io1);
 246
 247         writel(readl(&prcm_base->fclken1_core) |
 248                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 249                 &prcm_base->fclken1_core);
 250
 251         writel(readl(&prcm_base->iclken1_core) |
 252                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 253                 &prcm_base->iclken1_core);
 254 #endif
 255
 256 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 257         /* PBIAS config needed for MMC1 only */
 258         if (mmc_get_blk_desc(mmc)->devnum == 0)
 259                 vmmc_pbias_config(LDO_VOLT_3V0);
 260 #endif
 261
 262         return 0;
 263 }
 264
 265 void mmc_init_stream(struct hsmmc *mmc_base)
 266 {
 267         ulong start;
 268
 269         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 270
 271         writel(MMC_CMD0, &mmc_base->cmd);
 272         start = get_timer(0);
 273         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 274                 if (get_timer(0) - start > MAX_RETRY_MS) {
 275                         printf("%s: timedout waiting for cc!\n", __func__);
 276                         return;
 277                 }
 278         }
 279         writel(CC_MASK, &mmc_base->stat)
 280                 ;
 281         writel(MMC_CMD0, &mmc_base->cmd)
 282                 ;
 283         start = get_timer(0);
 284         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 285                 if (get_timer(0) - start > MAX_RETRY_MS) {
 286                         printf("%s: timedout waiting for cc2!\n", __func__);
 287                         return;
 288                 }
 289         }
 290         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 291 }
 292
 293 #if CONFIG_IS_ENABLED(DM_MMC)
 294 #ifdef CONFIG_IODELAY_RECALIBRATION
 295 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 296 {
 297         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 298         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 299
 300         switch (priv->mode) {
 301         case MMC_HS_200:
 302                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 303                 break;
 304         case UHS_SDR104:
 305                 pinctrl_state = priv->sdr104_pinctrl_state;
 306                 break;
 307         case UHS_SDR50:
 308                 pinctrl_state = priv->sdr50_pinctrl_state;
 309                 break;
 310         case UHS_DDR50:
 311                 pinctrl_state = priv->ddr50_pinctrl_state;
 312                 break;
 313         case UHS_SDR25:
 314                 pinctrl_state = priv->sdr25_pinctrl_state;
 315                 break;
 316         case UHS_SDR12:
 317                 pinctrl_state = priv->sdr12_pinctrl_state;
 318                 break;
 319         case SD_HS:
 320         case MMC_HS:
 321         case MMC_HS_52:
 322                 pinctrl_state = priv->hs_pinctrl_state;
 323                 break;
 324         case MMC_DDR_52:
 325                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 326         default:
 327                 pinctrl_state = priv->default_pinctrl_state;
 328                 break;
 329         }
 330
 331         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 332                 if (pinctrl_state->iodelay)
 333                         late_recalibrate_iodelay(pinctrl_state->padconf,
 334                                                  pinctrl_state->npads,
 335                                                  pinctrl_state->iodelay,
 336                                                  pinctrl_state->niodelays);
 337                 else
 338                         do_set_mux32((*ctrl)->control_padconf_core_base,
 339                                      pinctrl_state->padconf,
 340                                      pinctrl_state->npads);
 341         }
 342 }
 343 #endif
 344 static void omap_hsmmc_set_timing(struct mmc *mmc)
 345 {
 346         u32 val;
 347         struct hsmmc *mmc_base;
 348         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 349
 350         mmc_base = priv->base_addr;
 351
 352         omap_hsmmc_stop_clock(mmc_base);
 353         val = readl(&mmc_base->ac12);
 354         val &= ~AC12_UHSMC_MASK;
 355         priv->mode = mmc->selected_mode;
 356
 357         if (mmc_is_mode_ddr(priv->mode))
 358                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 359         else
 360                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 361
 362         switch (priv->mode) {
 363         case MMC_HS_200:
 364         case UHS_SDR104:
 365                 val |= AC12_UHSMC_SDR104;
 366                 break;
 367         case UHS_SDR50:
 368                 val |= AC12_UHSMC_SDR50;
 369                 break;
 370         case MMC_DDR_52:
 371         case UHS_DDR50:
 372                 val |= AC12_UHSMC_DDR50;
 373                 break;
 374         case SD_HS:
 375         case MMC_HS_52:
 376         case UHS_SDR25:
 377                 val |= AC12_UHSMC_SDR25;
 378                 break;
 379         case MMC_LEGACY:
 380         case MMC_HS:
 381         case SD_LEGACY:
 382         case UHS_SDR12:
 383                 val |= AC12_UHSMC_SDR12;
 384                 break;
 385         default:
 386                 val |= AC12_UHSMC_RES;
 387                 break;
 388         }
 389         writel(val, &mmc_base->ac12);
 390
 391 #ifdef CONFIG_IODELAY_RECALIBRATION
 392         omap_hsmmc_io_recalibrate(mmc);
 393 #endif
 394         omap_hsmmc_start_clock(mmc_base);
 395 }
 396
 397 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
 398 {
 399         struct hsmmc *mmc_base;
 400         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 401         u32 val;
 402
 403         mmc_base = priv->base_addr;
 404
 405         val = readl(&mmc_base->hctl) & ~SDVS_MASK;
 406
 407         switch (priv->iov) {
 408         case IOV_3V3:
 409                 val |= SDVS_3V3;
 410                 break;
 411         case IOV_3V0:
 412                 val |= SDVS_3V0;
 413                 break;
 414         case IOV_1V8:
 415                 val |= SDVS_1V8;
 416                 break;
 417         }
 418
 419         writel(val, &mmc_base->hctl);
 420 }
 421
 422 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 423 {
 424         struct hsmmc *mmc_base;
 425         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 426         u32 val;
 427
 428         mmc_base = priv->base_addr;
 429         val = readl(&mmc_base->capa);
 430
 431         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 432                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 433                 priv->iov = IOV_3V0;
 434         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 435                 val |= VS30_3V0SUP;
 436                 val &= ~VS18_1V8SUP;
 437                 priv->iov = IOV_3V0;
 438         } else {
 439                 val |= VS18_1V8SUP;
 440                 val &= ~VS30_3V0SUP;
 441                 priv->iov = IOV_1V8;
 442         }
 443
 444         writel(val, &mmc_base->capa);
 445 }
 446
 447 #ifdef MMC_SUPPORTS_TUNING
 448 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 449 {
 450         struct hsmmc *mmc_base;
 451         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 452         u32 val;
 453
 454         mmc_base = priv->base_addr;
 455         val = readl(&mmc_base->ac12);
 456         val &= ~(AC12_SCLK_SEL);
 457         writel(val, &mmc_base->ac12);
 458
 459         val = readl(&mmc_base->dll);
 460         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 461         writel(val, &mmc_base->dll);
 462 }
 463
 464 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 465 {
 466         int i;
 467         struct hsmmc *mmc_base;
 468         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 469         u32 val;
 470
 471         mmc_base = priv->base_addr;
 472         val = readl(&mmc_base->dll);
 473         val |= DLL_FORCE_VALUE;
 474         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 475         val |= (count << DLL_FORCE_SR_C_SHIFT);
 476         writel(val, &mmc_base->dll);
 477
 478         val |= DLL_CALIB;
 479         writel(val, &mmc_base->dll);
 480         for (i = 0; i < 1000; i++) {
 481                 if (readl(&mmc_base->dll) & DLL_CALIB)
 482                         break;
 483         }
 484         val &= ~DLL_CALIB;
 485         writel(val, &mmc_base->dll);
 486 }
 487
 488 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 489 {
 490         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 491         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 492         struct mmc *mmc = upriv->mmc;
 493         struct hsmmc *mmc_base;
 494         u32 val;
 495         u8 cur_match, prev_match = 0;
 496         int ret;
 497         u32 phase_delay = 0;
 498         u32 start_window = 0, max_window = 0;
 499         u32 length = 0, max_len = 0;
 500
 501         mmc_base = priv->base_addr;
 502         val = readl(&mmc_base->capa2);
 503
 504         /* clock tuning is not needed for upto 52MHz */
 505         if (!((mmc->selected_mode == MMC_HS_200) ||
 506               (mmc->selected_mode == UHS_SDR104) ||
 507               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 508                 return 0;
 509
 510         val = readl(&mmc_base->dll);
 511         val |= DLL_SWT;
 512         writel(val, &mmc_base->dll);
 513         while (phase_delay <= MAX_PHASE_DELAY) {
 514                 omap_hsmmc_set_dll(mmc, phase_delay);
 515
 516                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 517
 518                 if (cur_match) {
 519                         if (prev_match) {
 520                                 length++;
 521                         } else {
 522                                 start_window = phase_delay;
 523                                 length = 1;
 524                         }
 525                 }
 526
 527                 if (length > max_len) {
 528                         max_window = start_window;
 529                         max_len = length;
 530                 }
 531
 532                 prev_match = cur_match;
 533                 phase_delay += 4;
 534         }
 535
 536         if (!max_len) {
 537                 ret = -EIO;
 538                 goto tuning_error;
 539         }
 540
 541         val = readl(&mmc_base->ac12);
 542         if (!(val & AC12_SCLK_SEL)) {
 543                 ret = -EIO;
 544                 goto tuning_error;
 545         }
 546
 547         phase_delay = max_window + 4 * ((3 * max_len) >> 2);
 548         omap_hsmmc_set_dll(mmc, phase_delay);
 549
 550         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 551         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 552
 553         return 0;
 554
 555 tuning_error:
 556
 557         omap_hsmmc_disable_tuning(mmc);
 558         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 559         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 560
 561         return ret;
 562 }
 563 #endif
 564 #endif
 565
 566 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 567 {
 568         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 569         struct hsmmc *mmc_base = priv->base_addr;
 570         u32 irq_mask = INT_EN_MASK;
 571
 572         /*
 573          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 574          * tuning procedure and DCRC should be disabled. But see occurences
 575          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 576          * interrupts occur along with BRR, so the data is actually in the
 577          * buffer. It has to be debugged why these interrutps occur
 578          */
 579         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 580                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 581
 582         writel(irq_mask, &mmc_base->ie);
 583 }
 584
 585 static int omap_hsmmc_init_setup(struct mmc *mmc)
 586 {
 587         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 588         struct hsmmc *mmc_base;
 589         unsigned int reg_val;
 590         unsigned int dsor;
 591         ulong start;
 592
 593         mmc_base = priv->base_addr;
 594         mmc_board_init(mmc);
 595
 596         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 597                 &mmc_base->sysconfig);
 598         start = get_timer(0);
 599         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 600                 if (get_timer(0) - start > MAX_RETRY_MS) {
 601                         printf("%s: timedout waiting for cc2!\n", __func__);
 602                         return -ETIMEDOUT;
 603                 }
 604         }
 605         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 606         start = get_timer(0);
 607         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 608                 if (get_timer(0) - start > MAX_RETRY_MS) {
 609                         printf("%s: timedout waiting for softresetall!\n",
 610                                 __func__);
 611                         return -ETIMEDOUT;
 612                 }
 613         }
 614 #ifndef CONFIG_OMAP34XX
 615         reg_val = readl(&mmc_base->hl_hwinfo);
 616         if (reg_val & MADMA_EN)
 617                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 618 #endif
 619
 620 #if CONFIG_IS_ENABLED(DM_MMC)
 621         omap_hsmmc_set_capabilities(mmc);
 622         omap_hsmmc_conf_bus_power(mmc);
 623 #else
 624         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 625         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 626                 &mmc_base->capa);
 627 #endif
 628
 629         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 630
 631         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 632                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 633                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 634
 635         dsor = 240;
 636         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 637                 (ICE_STOP | DTO_15THDTO));
 638         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 639                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 640         start = get_timer(0);
 641         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 642                 if (get_timer(0) - start > MAX_RETRY_MS) {
 643                         printf("%s: timedout waiting for ics!\n", __func__);
 644                         return -ETIMEDOUT;
 645                 }
 646         }
 647         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 648
 649         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 650
 651         mmc_enable_irq(mmc, NULL);
 652         mmc_init_stream(mmc_base);
 653
 654         return 0;
 655 }
 656
 657 /*
 658  * MMC controller internal finite state machine reset
 659  *
 660  * Used to reset command or data internal state machines, using respectively
 661  * SRC or SRD bit of SYSCTL register
 662  */
 663 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 664 {
 665         ulong start;
 666
 667         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 668
 669         /*
 670          * CMD(DAT) lines reset procedures are slightly different
 671          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 672          * According to OMAP3 TRM:
 673          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 674          * returns to 0x0.
 675          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 676          * procedure steps must be as follows:
 677          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 678          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 679          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 680          * 3. Wait until the SRC (SRD) bit returns to 0x0
 681          *    (reset procedure is completed).
 682          */
 683 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 684         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 685         if (!(readl(&mmc_base->sysctl) & bit)) {
 686                 start = get_timer(0);
 687                 while (!(readl(&mmc_base->sysctl) & bit)) {
 688                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 689                                 return;
 690                 }
 691         }
 692 #endif
 693         start = get_timer(0);
 694         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 695                 if (get_timer(0) - start > MAX_RETRY_MS) {
 696                         printf("%s: timedout waiting for sysctl %x to clear\n",
 697                                 __func__, bit);
 698                         return;
 699                 }
 700         }
 701 }
 702
 703 #ifndef CONFIG_OMAP34XX
 704 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 705 {
 706         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 707         struct omap_hsmmc_adma_desc *desc;
 708         u8 attr;
 709
 710         desc = &priv->adma_desc_table[priv->desc_slot];
 711
 712         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 713         if (!end)
 714                 priv->desc_slot++;
 715         else
 716                 attr |= ADMA_DESC_ATTR_END;
 717
 718         desc->len = len;
 719         desc->addr = (u32)buf;
 720         desc->reserved = 0;
 721         desc->attr = attr;
 722 }
 723
 724 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 725                                           struct mmc_data *data)
 726 {
 727         uint total_len = data->blocksize * data->blocks;
 728         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 729         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 730         int i = desc_count;
 731         char *buf;
 732
 733         priv->desc_slot = 0;
 734         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 735                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 736                                 sizeof(struct omap_hsmmc_adma_desc));
 737
 738         if (data->flags & MMC_DATA_READ)
 739                 buf = data->dest;
 740         else
 741                 buf = (char *)data->src;
 742
 743         while (--i) {
 744                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 745                 buf += ADMA_MAX_LEN;
 746                 total_len -= ADMA_MAX_LEN;
 747         }
 748
 749         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 750
 751         flush_dcache_range((long)priv->adma_desc_table,
 752                            (long)priv->adma_desc_table +
 753                            ROUND(desc_count *
 754                            sizeof(struct omap_hsmmc_adma_desc),
 755                            ARCH_DMA_MINALIGN));
 756 }
 757
 758 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 759 {
 760         struct hsmmc *mmc_base;
 761         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 762         u32 val;
 763         char *buf;
 764
 765         mmc_base = priv->base_addr;
 766         omap_hsmmc_prepare_adma_table(mmc, data);
 767
 768         if (data->flags & MMC_DATA_READ)
 769                 buf = data->dest;
 770         else
 771                 buf = (char *)data->src;
 772
 773         val = readl(&mmc_base->hctl);
 774         val |= DMA_SELECT;
 775         writel(val, &mmc_base->hctl);
 776
 777         val = readl(&mmc_base->con);
 778         val |= DMA_MASTER;
 779         writel(val, &mmc_base->con);
 780
 781         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 782
 783         flush_dcache_range((u32)buf,
 784                            (u32)buf +
 785                            ROUND(data->blocksize * data->blocks,
 786                                  ARCH_DMA_MINALIGN));
 787 }
 788
 789 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
 790 {
 791         struct hsmmc *mmc_base;
 792         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 793         u32 val;
 794
 795         mmc_base = priv->base_addr;
 796
 797         val = readl(&mmc_base->con);
 798         val &= ~DMA_MASTER;
 799         writel(val, &mmc_base->con);
 800
 801         val = readl(&mmc_base->hctl);
 802         val &= ~DMA_SELECT;
 803         writel(val, &mmc_base->hctl);
 804
 805         kfree(priv->adma_desc_table);
 806 }
 807 #else
 808 #define omap_hsmmc_adma_desc
 809 #define omap_hsmmc_prepare_adma_table
 810 #define omap_hsmmc_prepare_data
 811 #define omap_hsmmc_dma_cleanup
 812 #endif
 813
 814 #if !CONFIG_IS_ENABLED(DM_MMC)
 815 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 816                         struct mmc_data *data)
 817 {
 818         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 819 #else
 820 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 821                         struct mmc_data *data)
 822 {
 823         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 824         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 825         struct mmc *mmc = upriv->mmc;
 826 #endif
 827         struct hsmmc *mmc_base;
 828         unsigned int flags, mmc_stat;
 829         ulong start;
 830
 831         mmc_base = priv->base_addr;
 832
 833         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 834                 return 0;
 835
 836         start = get_timer(0);
 837         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 838                 if (get_timer(0) - start > MAX_RETRY_MS) {
 839                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 840                                         __func__);
 841                         return -ETIMEDOUT;
 842                 }
 843         }
 844         writel(0xFFFFFFFF, &mmc_base->stat);
 845         start = get_timer(0);
 846         while (readl(&mmc_base->stat)) {
 847                 if (get_timer(0) - start > MAX_RETRY_MS) {
 848                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 849                                 __func__, readl(&mmc_base->stat));
 850                         return -ETIMEDOUT;
 851                 }
 852         }
 853         /*
 854          * CMDREG
 855          * CMDIDX[13:8] : Command index
 856          * DATAPRNT[5]  : Data Present Select
 857          * ENCMDIDX[4]  : Command Index Check Enable
 858          * ENCMDCRC[3]  : Command CRC Check Enable
 859          * RSPTYP[1:0]
 860          *      00 = No Response
 861          *      01 = Length 136
 862          *      10 = Length 48
 863          *      11 = Length 48 Check busy after response
 864          */
 865         /* Delay added before checking the status of frq change
 866          * retry not supported by mmc.c(core file)
 867          */
 868         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 869                 udelay(50000); /* wait 50 ms */
 870
 871         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 872                 flags = 0;
 873         else if (cmd->resp_type & MMC_RSP_136)
 874                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 875         else if (cmd->resp_type & MMC_RSP_BUSY)
 876                 flags = RSP_TYPE_LGHT48B;
 877         else
 878                 flags = RSP_TYPE_LGHT48;
 879
 880         /* enable default flags */
 881         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 882                         MSBS_SGLEBLK);
 883         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 884
 885         if (cmd->resp_type & MMC_RSP_CRC)
 886                 flags |= CCCE_CHECK;
 887         if (cmd->resp_type & MMC_RSP_OPCODE)
 888                 flags |= CICE_CHECK;
 889
 890         if (data) {
 891                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 892                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 893                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
 894                         data->blocksize = 512;
 895                         writel(data->blocksize | (data->blocks << 16),
 896                                                         &mmc_base->blk);
 897                 } else
 898                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 899
 900                 if (data->flags & MMC_DATA_READ)
 901                         flags |= (DP_DATA | DDIR_READ);
 902                 else
 903                         flags |= (DP_DATA | DDIR_WRITE);
 904
 905 #ifndef CONFIG_OMAP34XX
 906                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
 907                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
 908                         omap_hsmmc_prepare_data(mmc, data);
 909                         flags |= DE_ENABLE;
 910                 }
 911 #endif
 912         }
 913
 914         mmc_enable_irq(mmc, cmd);
 915
 916         writel(cmd->cmdarg, &mmc_base->arg);
 917         udelay(20);             /* To fix "No status update" error on eMMC */
 918         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 919
 920         start = get_timer(0);
 921         do {
 922                 mmc_stat = readl(&mmc_base->stat);
 923                 if (get_timer(start) > MAX_RETRY_MS) {
 924                         printf("%s : timeout: No status update\n", __func__);
 925                         return -ETIMEDOUT;
 926                 }
 927         } while (!mmc_stat);
 928
 929         if ((mmc_stat & IE_CTO) != 0) {
 930                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 931                 return -ETIMEDOUT;
 932         } else if ((mmc_stat & ERRI_MASK) != 0)
 933                 return -1;
 934
 935         if (mmc_stat & CC_MASK) {
 936                 writel(CC_MASK, &mmc_base->stat);
 937                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 938                         if (cmd->resp_type & MMC_RSP_136) {
 939                                 /* response type 2 */
 940                                 cmd->response[3] = readl(&mmc_base->rsp10);
 941                                 cmd->response[2] = readl(&mmc_base->rsp32);
 942                                 cmd->response[1] = readl(&mmc_base->rsp54);
 943                                 cmd->response[0] = readl(&mmc_base->rsp76);
 944                         } else
 945                                 /* response types 1, 1b, 3, 4, 5, 6 */
 946                                 cmd->response[0] = readl(&mmc_base->rsp10);
 947                 }
 948         }
 949
 950 #ifndef CONFIG_OMAP34XX
 951         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
 952             !mmc_is_tuning_cmd(cmd->cmdidx)) {
 953                 u32 sz_mb, timeout;
 954
 955                 if (mmc_stat & IE_ADMAE) {
 956                         omap_hsmmc_dma_cleanup(mmc);
 957                         return -EIO;
 958                 }
 959
 960                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
 961                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
 962                 if (timeout < MAX_RETRY_MS)
 963                         timeout = MAX_RETRY_MS;
 964
 965                 start = get_timer(0);
 966                 do {
 967                         mmc_stat = readl(&mmc_base->stat);
 968                         if (mmc_stat & TC_MASK) {
 969                                 writel(readl(&mmc_base->stat) | TC_MASK,
 970                                        &mmc_base->stat);
 971                                 break;
 972                         }
 973                         if (get_timer(start) > timeout) {
 974                                 printf("%s : DMA timeout: No status update\n",
 975                                        __func__);
 976                                 return -ETIMEDOUT;
 977                         }
 978                 } while (1);
 979
 980                 omap_hsmmc_dma_cleanup(mmc);
 981                 return 0;
 982         }
 983 #endif
 984
 985         if (data && (data->flags & MMC_DATA_READ)) {
 986                 mmc_read_data(mmc_base, data->dest,
 987                                 data->blocksize * data->blocks);
 988         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 989                 mmc_write_data(mmc_base, data->src,
 990                                 data->blocksize * data->blocks);
 991         }
 992         return 0;
 993 }
 994
 995 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 996 {
 997         unsigned int *output_buf = (unsigned int *)buf;
 998         unsigned int mmc_stat;
 999         unsigned int count;
1000
1001         /*
1002          * Start Polled Read
1003          */
1004         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1005         count /= 4;
1006
1007         while (size) {
1008                 ulong start = get_timer(0);
1009                 do {
1010                         mmc_stat = readl(&mmc_base->stat);
1011                         if (get_timer(0) - start > MAX_RETRY_MS) {
1012                                 printf("%s: timedout waiting for status!\n",
1013                                                 __func__);
1014                                 return -ETIMEDOUT;
1015                         }
1016                 } while (mmc_stat == 0);
1017
1018                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1019                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1020
1021                 if ((mmc_stat & ERRI_MASK) != 0)
1022                         return 1;
1023
1024                 if (mmc_stat & BRR_MASK) {
1025                         unsigned int k;
1026
1027                         writel(readl(&mmc_base->stat) | BRR_MASK,
1028                                 &mmc_base->stat);
1029                         for (k = 0; k < count; k++) {
1030                                 *output_buf = readl(&mmc_base->data);
1031                                 output_buf++;
1032                         }
1033                         size -= (count*4);
1034                 }
1035
1036                 if (mmc_stat & BWR_MASK)
1037                         writel(readl(&mmc_base->stat) | BWR_MASK,
1038                                 &mmc_base->stat);
1039
1040                 if (mmc_stat & TC_MASK) {
1041                         writel(readl(&mmc_base->stat) | TC_MASK,
1042                                 &mmc_base->stat);
1043                         break;
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1050                                 unsigned int size)
1051 {
1052         unsigned int *input_buf = (unsigned int *)buf;
1053         unsigned int mmc_stat;
1054         unsigned int count;
1055
1056         /*
1057          * Start Polled Write
1058          */
1059         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1060         count /= 4;
1061
1062         while (size) {
1063                 ulong start = get_timer(0);
1064                 do {
1065                         mmc_stat = readl(&mmc_base->stat);
1066                         if (get_timer(0) - start > MAX_RETRY_MS) {
1067                                 printf("%s: timedout waiting for status!\n",
1068                                                 __func__);
1069                                 return -ETIMEDOUT;
1070                         }
1071                 } while (mmc_stat == 0);
1072
1073                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1074                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1075
1076                 if ((mmc_stat & ERRI_MASK) != 0)
1077                         return 1;
1078
1079                 if (mmc_stat & BWR_MASK) {
1080                         unsigned int k;
1081
1082                         writel(readl(&mmc_base->stat) | BWR_MASK,
1083                                         &mmc_base->stat);
1084                         for (k = 0; k < count; k++) {
1085                                 writel(*input_buf, &mmc_base->data);
1086                                 input_buf++;
1087                         }
1088                         size -= (count*4);
1089                 }
1090
1091                 if (mmc_stat & BRR_MASK)
1092                         writel(readl(&mmc_base->stat) | BRR_MASK,
1093                                 &mmc_base->stat);
1094
1095                 if (mmc_stat & TC_MASK) {
1096                         writel(readl(&mmc_base->stat) | TC_MASK,
1097                                 &mmc_base->stat);
1098                         break;
1099                 }
1100         }
1101         return 0;
1102 }
1103
1104 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1105 {
1106         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1107 }
1108
1109 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1110 {
1111         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1112 }
1113
1114 static void omap_hsmmc_set_clock(struct mmc *mmc)
1115 {
1116         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1117         struct hsmmc *mmc_base;
1118         unsigned int dsor = 0;
1119         ulong start;
1120
1121         mmc_base = priv->base_addr;
1122         omap_hsmmc_stop_clock(mmc_base);
1123
1124         /* TODO: Is setting DTO required here? */
1125         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1126                     (ICE_STOP | DTO_15THDTO));
1127
1128         if (mmc->clock != 0) {
1129                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1130                 if (dsor > CLKD_MAX)
1131                         dsor = CLKD_MAX;
1132         } else {
1133                 dsor = CLKD_MAX;
1134         }
1135
1136         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1137                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1138
1139         start = get_timer(0);
1140         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1141                 if (get_timer(0) - start > MAX_RETRY_MS) {
1142                         printf("%s: timedout waiting for ics!\n", __func__);
1143                         return;
1144                 }
1145         }
1146
1147         priv->clock = mmc->clock;
1148         omap_hsmmc_start_clock(mmc_base);
1149 }
1150
1151 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1152 {
1153         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1154         struct hsmmc *mmc_base;
1155
1156         mmc_base = priv->base_addr;
1157         /* configue bus width */
1158         switch (mmc->bus_width) {
1159         case 8:
1160                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1161                         &mmc_base->con);
1162                 break;
1163
1164         case 4:
1165                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1166                         &mmc_base->con);
1167                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1168                         &mmc_base->hctl);
1169                 break;
1170
1171         case 1:
1172         default:
1173                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1174                         &mmc_base->con);
1175                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1176                         &mmc_base->hctl);
1177                 break;
1178         }
1179
1180         priv->bus_width = mmc->bus_width;
1181 }
1182
1183 #if !CONFIG_IS_ENABLED(DM_MMC)
1184 static int omap_hsmmc_set_ios(struct mmc *mmc)
1185 {
1186         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1187 #else
1188 static int omap_hsmmc_set_ios(struct udevice *dev)
1189 {
1190         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1191         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1192         struct mmc *mmc = upriv->mmc;
1193 #endif
1194
1195         if (priv->bus_width != mmc->bus_width)
1196                 omap_hsmmc_set_bus_width(mmc);
1197
1198         if (priv->clock != mmc->clock)
1199                 omap_hsmmc_set_clock(mmc);
1200
1201 #if CONFIG_IS_ENABLED(DM_MMC)
1202         if (priv->mode != mmc->selected_mode)
1203                 omap_hsmmc_set_timing(mmc);
1204 #endif
1205         return 0;
1206 }
1207
1208 #ifdef OMAP_HSMMC_USE_GPIO
1209 #if CONFIG_IS_ENABLED(DM_MMC)
1210 static int omap_hsmmc_getcd(struct udevice *dev)
1211 {
1212         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1213         int value;
1214
1215         value = dm_gpio_get_value(&priv->cd_gpio);
1216         /* if no CD return as 1 */
1217         if (value < 0)
1218                 return 1;
1219
1220         if (priv->cd_inverted)
1221                 return !value;
1222         return value;
1223 }
1224
1225 static int omap_hsmmc_getwp(struct udevice *dev)
1226 {
1227         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1228         int value;
1229
1230         value = dm_gpio_get_value(&priv->wp_gpio);
1231         /* if no WP return as 0 */
1232         if (value < 0)
1233                 return 0;
1234         return value;
1235 }
1236 #else
1237 static int omap_hsmmc_getcd(struct mmc *mmc)
1238 {
1239         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1240         int cd_gpio;
1241
1242         /* if no CD return as 1 */
1243         cd_gpio = priv->cd_gpio;
1244         if (cd_gpio < 0)
1245                 return 1;
1246
1247         /* NOTE: assumes card detect signal is active-low */
1248         return !gpio_get_value(cd_gpio);
1249 }
1250
1251 static int omap_hsmmc_getwp(struct mmc *mmc)
1252 {
1253         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1254         int wp_gpio;
1255
1256         /* if no WP return as 0 */
1257         wp_gpio = priv->wp_gpio;
1258         if (wp_gpio < 0)
1259                 return 0;
1260
1261         /* NOTE: assumes write protect signal is active-high */
1262         return gpio_get_value(wp_gpio);
1263 }
1264 #endif
1265 #endif
1266
1267 #if CONFIG_IS_ENABLED(DM_MMC)
1268 static const struct dm_mmc_ops omap_hsmmc_ops = {
1269         .send_cmd       = omap_hsmmc_send_cmd,
1270         .set_ios        = omap_hsmmc_set_ios,
1271 #ifdef OMAP_HSMMC_USE_GPIO
1272         .get_cd         = omap_hsmmc_getcd,
1273         .get_wp         = omap_hsmmc_getwp,
1274 #endif
1275 #ifdef MMC_SUPPORTS_TUNING
1276         .execute_tuning = omap_hsmmc_execute_tuning,
1277 #endif
1278 };
1279 #else
1280 static const struct mmc_ops omap_hsmmc_ops = {
1281         .send_cmd       = omap_hsmmc_send_cmd,
1282         .set_ios        = omap_hsmmc_set_ios,
1283         .init           = omap_hsmmc_init_setup,
1284 #ifdef OMAP_HSMMC_USE_GPIO
1285         .getcd          = omap_hsmmc_getcd,
1286         .getwp          = omap_hsmmc_getwp,
1287 #endif
1288 };
1289 #endif
1290
1291 #if !CONFIG_IS_ENABLED(DM_MMC)
1292 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1293                 int wp_gpio)
1294 {
1295         struct mmc *mmc;
1296         struct omap_hsmmc_data *priv;
1297         struct mmc_config *cfg;
1298         uint host_caps_val;
1299
1300         priv = malloc(sizeof(*priv));
1301         if (priv == NULL)
1302                 return -1;
1303
1304         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1305
1306         switch (dev_index) {
1307         case 0:
1308                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1309                 break;
1310 #ifdef OMAP_HSMMC2_BASE
1311         case 1:
1312                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1313 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1314         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1315         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1316                 defined(CONFIG_HSMMC2_8BIT)
1317                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1318                 host_caps_val |= MMC_MODE_8BIT;
1319 #endif
1320                 break;
1321 #endif
1322 #ifdef OMAP_HSMMC3_BASE
1323         case 2:
1324                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1325 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1326                 /* Enable 8-bit interface for eMMC on DRA7XX */
1327                 host_caps_val |= MMC_MODE_8BIT;
1328 #endif
1329                 break;
1330 #endif
1331         default:
1332                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1333                 return 1;
1334         }
1335 #ifdef OMAP_HSMMC_USE_GPIO
1336         /* on error gpio values are set to -1, which is what we want */
1337         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1338         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1339 #endif
1340
1341         cfg = &priv->cfg;
1342
1343         cfg->name = "OMAP SD/MMC";
1344         cfg->ops = &omap_hsmmc_ops;
1345
1346         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1347         cfg->host_caps = host_caps_val & ~host_caps_mask;
1348
1349         cfg->f_min = 400000;
1350
1351         if (f_max != 0)
1352                 cfg->f_max = f_max;
1353         else {
1354                 if (cfg->host_caps & MMC_MODE_HS) {
1355                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1356                                 cfg->f_max = 52000000;
1357                         else
1358                                 cfg->f_max = 26000000;
1359                 } else
1360                         cfg->f_max = 20000000;
1361         }
1362
1363         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1364
1365 #if defined(CONFIG_OMAP34XX)
1366         /*
1367          * Silicon revs 2.1 and older do not support multiblock transfers.
1368          */
1369         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1370                 cfg->b_max = 1;
1371 #endif
1372
1373         mmc = mmc_create(cfg, priv);
1374         if (mmc == NULL)
1375                 return -1;
1376
1377         return 0;
1378 }
1379 #else
1380
1381 #ifdef CONFIG_IODELAY_RECALIBRATION
1382 static struct pad_conf_entry *
1383 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1384 {
1385         int index = 0;
1386         struct pad_conf_entry *padconf;
1387
1388         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1389         if (!padconf) {
1390                 debug("failed to allocate memory\n");
1391                 return 0;
1392         }
1393
1394         while (index < count) {
1395                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1396                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1397                 index++;
1398         }
1399
1400         return padconf;
1401 }
1402
1403 static struct iodelay_cfg_entry *
1404 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1405 {
1406         int index = 0;
1407         struct iodelay_cfg_entry *iodelay;
1408
1409         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1410         if (!iodelay) {
1411                 debug("failed to allocate memory\n");
1412                 return 0;
1413         }
1414
1415         while (index < count) {
1416                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1417                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1418                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1419                 index++;
1420         }
1421
1422         return iodelay;
1423 }
1424
1425 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1426                                                    const char *name, int *len)
1427 {
1428         const void *fdt = gd->fdt_blob;
1429         int offset;
1430         const fdt32_t *pinctrl;
1431
1432         offset = fdt_node_offset_by_phandle(fdt, phandle);
1433         if (offset < 0) {
1434                 debug("failed to get pinctrl node %s.\n",
1435                       fdt_strerror(offset));
1436                 return 0;
1437         }
1438
1439         pinctrl = fdt_getprop(fdt, offset, name, len);
1440         if (!pinctrl) {
1441                 debug("failed to get property %s\n", name);
1442                 return 0;
1443         }
1444
1445         return pinctrl;
1446 }
1447
1448 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1449                                                 char *prop_name)
1450 {
1451         const void *fdt = gd->fdt_blob;
1452         const __be32 *phandle;
1453         int node = dev_of_offset(mmc->dev);
1454
1455         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1456         if (!phandle) {
1457                 debug("failed to get property %s\n", prop_name);
1458                 return 0;
1459         }
1460
1461         return fdt32_to_cpu(*phandle);
1462 }
1463
1464 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1465                                                char *prop_name)
1466 {
1467         const void *fdt = gd->fdt_blob;
1468         const __be32 *phandle;
1469         int len;
1470         int count;
1471         int node = dev_of_offset(mmc->dev);
1472
1473         phandle = fdt_getprop(fdt, node, prop_name, &len);
1474         if (!phandle) {
1475                 debug("failed to get property %s\n", prop_name);
1476                 return 0;
1477         }
1478
1479         /* No manual mode iodelay values if count < 2 */
1480         count = len / sizeof(*phandle);
1481         if (count < 2)
1482                 return 0;
1483
1484         return fdt32_to_cpu(*(phandle + 1));
1485 }
1486
1487 static struct pad_conf_entry *
1488 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1489 {
1490         int len;
1491         int count;
1492         struct pad_conf_entry *padconf;
1493         u32 phandle;
1494         const fdt32_t *pinctrl;
1495
1496         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1497         if (!phandle)
1498                 return ERR_PTR(-EINVAL);
1499
1500         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1501                                                &len);
1502         if (!pinctrl)
1503                 return ERR_PTR(-EINVAL);
1504
1505         count = (len / sizeof(*pinctrl)) / 2;
1506         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1507         if (!padconf)
1508                 return ERR_PTR(-EINVAL);
1509
1510         *npads = count;
1511
1512         return padconf;
1513 }
1514
1515 static struct iodelay_cfg_entry *
1516 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1517 {
1518         int len;
1519         int count;
1520         struct iodelay_cfg_entry *iodelay;
1521         u32 phandle;
1522         const fdt32_t *pinctrl;
1523
1524         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1525         /* Not all modes have manual mode iodelay values. So its not fatal */
1526         if (!phandle)
1527                 return 0;
1528
1529         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1530                                                &len);
1531         if (!pinctrl)
1532                 return ERR_PTR(-EINVAL);
1533
1534         count = (len / sizeof(*pinctrl)) / 3;
1535         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1536         if (!iodelay)
1537                 return ERR_PTR(-EINVAL);
1538
1539         *niodelay = count;
1540
1541         return iodelay;
1542 }
1543
1544 static struct omap_hsmmc_pinctrl_state *
1545 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1546 {
1547         int index;
1548         int npads = 0;
1549         int niodelays = 0;
1550         const void *fdt = gd->fdt_blob;
1551         int node = dev_of_offset(mmc->dev);
1552         char prop_name[11];
1553         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1554
1555         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1556                          malloc(sizeof(*pinctrl_state));
1557         if (!pinctrl_state) {
1558                 debug("failed to allocate memory\n");
1559                 return 0;
1560         }
1561
1562         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1563         if (index < 0) {
1564                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1565                 goto err_pinctrl_state;
1566         }
1567
1568         sprintf(prop_name, "pinctrl-%d", index);
1569
1570         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1571                                                          &npads);
1572         if (IS_ERR(pinctrl_state->padconf))
1573                 goto err_pinctrl_state;
1574         pinctrl_state->npads = npads;
1575
1576         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1577                                                         &niodelays);
1578         if (IS_ERR(pinctrl_state->iodelay))
1579                 goto err_padconf;
1580         pinctrl_state->niodelays = niodelays;
1581
1582         return pinctrl_state;
1583
1584 err_padconf:
1585         kfree(pinctrl_state->padconf);
1586
1587 err_pinctrl_state:
1588         kfree(pinctrl_state);
1589         return 0;
1590 }
1591
1592 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)                         \
1593         do {                                                            \
1594                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1595                 char str[20];                                           \
1596                 if (!(cfg->host_caps & capmask))                        \
1597                         break;                                          \
1598                                                                         \
1599                 if (priv->hw_rev) {                                     \
1600                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1601                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1602                 }                                                       \
1603                                                                         \
1604                 if (!s)                                                 \
1605                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1606                                                                         \
1607                 if (!s) {                                               \
1608                         debug("%s: no pinctrl for %s\n",                \
1609                               mmc->dev->name, #mode);                   \
1610                         cfg->host_caps &= ~(capmask);                   \
1611                 } else {                                                \
1612                         priv->mode##_pinctrl_state = s;                 \
1613                 }                                                       \
1614         } while (0)
1615
1616 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1617 {
1618         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1619         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1620         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1621
1622         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1623                 return 0;
1624
1625         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1626         if (!default_pinctrl) {
1627                 printf("no pinctrl state for default mode\n");
1628                 return -EINVAL;
1629         }
1630
1631         priv->default_pinctrl_state = default_pinctrl;
1632
1633         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104);
1634         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50);
1635         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50);
1636         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25);
1637         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12);
1638
1639         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v);
1640         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v);
1641         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs);
1642
1643         return 0;
1644 }
1645 #endif
1646
1647 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1648 #ifdef CONFIG_OMAP54XX
1649 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1650 {
1651         return NULL;
1652 }
1653 #endif
1654
1655 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1656 {
1657         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1658         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1659
1660         struct mmc_config *cfg = &plat->cfg;
1661 #ifdef CONFIG_OMAP54XX
1662         const struct mmc_platform_fixups *fixups;
1663 #endif
1664         const void *fdt = gd->fdt_blob;
1665         int node = dev_of_offset(dev);
1666         int ret;
1667
1668         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1669                                       sizeof(struct hsmmc *),
1670                                       MAP_NOCACHE);
1671
1672         ret = mmc_of_parse(dev, cfg);
1673         if (ret < 0)
1674                 return ret;
1675
1676         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1677         cfg->f_min = 400000;
1678         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1679         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1680         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1681                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1682         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1683                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1684         if (of_data)
1685                 plat->controller_flags |= of_data->controller_flags;
1686
1687 #ifdef CONFIG_OMAP54XX
1688         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1689         if (fixups) {
1690                 plat->hw_rev = fixups->hw_rev;
1691                 cfg->host_caps &= ~fixups->unsupported_caps;
1692                 cfg->f_max = fixups->max_freq;
1693         }
1694 #endif
1695
1696 #ifdef OMAP_HSMMC_USE_GPIO
1697         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1698 #endif
1699
1700         return 0;
1701 }
1702 #endif
1703
1704 #ifdef CONFIG_BLK
1705
1706 static int omap_hsmmc_bind(struct udevice *dev)
1707 {
1708         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1709
1710         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1711 }
1712 #endif
1713 static int omap_hsmmc_probe(struct udevice *dev)
1714 {
1715         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1716         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1717         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1718         struct mmc_config *cfg = &plat->cfg;
1719         struct mmc *mmc;
1720 #ifdef CONFIG_IODELAY_RECALIBRATION
1721         int ret;
1722 #endif
1723
1724         cfg->name = "OMAP SD/MMC";
1725         priv->base_addr = plat->base_addr;
1726         priv->controller_flags = plat->controller_flags;
1727         priv->hw_rev = plat->hw_rev;
1728 #ifdef OMAP_HSMMC_USE_GPIO
1729         priv->cd_inverted = plat->cd_inverted;
1730 #endif
1731
1732 #ifdef CONFIG_BLK
1733         mmc = &plat->mmc;
1734 #else
1735         mmc = mmc_create(cfg, priv);
1736         if (mmc == NULL)
1737                 return -1;
1738 #endif
1739
1740 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1741         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1742         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1743 #endif
1744
1745         mmc->dev = dev;
1746         upriv->mmc = mmc;
1747
1748 #ifdef CONFIG_IODELAY_RECALIBRATION
1749         ret = omap_hsmmc_get_pinctrl_state(mmc);
1750         /*
1751          * disable high speed modes for the platforms that require IO delay
1752          * and for which we don't have this information
1753          */
1754         if ((ret < 0) &&
1755             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1756                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1757                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1758                                     UHS_CAPS);
1759         }
1760 #endif
1761
1762         return omap_hsmmc_init_setup(mmc);
1763 }
1764
1765 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1766
1767 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1768         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1769 };
1770
1771 static const struct udevice_id omap_hsmmc_ids[] = {
1772         { .compatible = "ti,omap3-hsmmc" },
1773         { .compatible = "ti,omap4-hsmmc" },
1774         { .compatible = "ti,am33xx-hsmmc" },
1775         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1776         { }
1777 };
1778 #endif
1779
1780 U_BOOT_DRIVER(omap_hsmmc) = {
1781         .name   = "omap_hsmmc",
1782         .id     = UCLASS_MMC,
1783 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1784         .of_match = omap_hsmmc_ids,
1785         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1786         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1787 #endif
1788 #ifdef CONFIG_BLK
1789         .bind = omap_hsmmc_bind,
1790 #endif
1791         .ops = &omap_hsmmc_ops,
1792         .probe  = omap_hsmmc_probe,
1793         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1794         .flags  = DM_FLAG_PRE_RELOC,
1795 };
1796 #endif