git.sur5r.net Git - u-boot/blob - drivers/mmc/socfpga_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/clock_manager.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <dm.h>
  10 #include <dwmmc.h>
  11 #include <errno.h>
  12 #include <fdtdec.h>
  13 #include <linux/libfdt.h>
  14 #include <linux/err.h>
  15 #include <malloc.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static const struct socfpga_clock_manager *clock_manager_base =
  20                 (void *)SOCFPGA_CLKMGR_ADDRESS;
  21 static const struct socfpga_system_manager *system_manager_base =
  22                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  23
  24 struct socfpga_dwmci_plat {
  25         struct mmc_config cfg;
  26         struct mmc mmc;
  27 };
  28
  29 /* socfpga implmentation specific driver private data */
  30 struct dwmci_socfpga_priv_data {
  31         struct dwmci_host       host;
  32         unsigned int            drvsel;
  33         unsigned int            smplsel;
  34 };
  35
  36 static void socfpga_dwmci_clksel(struct dwmci_host *host)
  37 {
  38         struct dwmci_socfpga_priv_data *priv = host->priv;
  39         u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  40                          ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  41
  42         /* Disable SDMMC clock. */
  43         clrbits_le32(&clock_manager_base->per_pll.en,
  44                 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  45
  46         debug("%s: drvsel %d smplsel %d\n", __func__,
  47               priv->drvsel, priv->smplsel);
  48         writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
  49
  50         debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  51                 readl(&system_manager_base->sdmmcgrp_ctrl));
  52
  53         /* Enable SDMMC clock */
  54         setbits_le32(&clock_manager_base->per_pll.en,
  55                 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  56 }
  57
  58 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
  59 {
  60         /* FIXME: probe from DT eventually too/ */
  61         const unsigned long clk = cm_get_mmc_controller_clk_hz();
  62
  63         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  64         struct dwmci_host *host = &priv->host;
  65         int fifo_depth;
  66
  67         if (clk == 0) {
  68                 printf("DWMMC: MMC clock is zero!");
  69                 return -EINVAL;
  70         }
  71
  72         fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  73                                     "fifo-depth", 0);
  74         if (fifo_depth < 0) {
  75                 printf("DWMMC: Can't get FIFO depth\n");
  76                 return -EINVAL;
  77         }
  78
  79         host->name = dev->name;
  80         host->ioaddr = (void *)devfdt_get_addr(dev);
  81         host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  82                                         "bus-width", 4);
  83         host->clksel = socfpga_dwmci_clksel;
  84
  85         /*
  86          * TODO(sjg@chromium.org): Remove the need for this hack.
  87          * We only have one dwmmc block on gen5 SoCFPGA.
  88          */
  89         host->dev_index = 0;
  90         /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  91         host->bus_hz = clk;
  92         host->fifoth_val = MSIZE(0x2) |
  93                 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
  94         priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  95                                        "drvsel", 3);
  96         priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  97                                         "smplsel", 0);
  98         host->priv = priv;
  99
 100         return 0;
 101 }
 102
 103 static int socfpga_dwmmc_probe(struct udevice *dev)
 104 {
 105 #ifdef CONFIG_BLK
 106         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 107 #endif
 108         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 109         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 110         struct dwmci_host *host = &priv->host;
 111
 112 #ifdef CONFIG_BLK
 113         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
 114         host->mmc = &plat->mmc;
 115 #else
 116         int ret;
 117
 118         ret = add_dwmci(host, host->bus_hz, 400000);
 119         if (ret)
 120                 return ret;
 121 #endif
 122         host->mmc->priv = &priv->host;
 123         upriv->mmc = host->mmc;
 124         host->mmc->dev = dev;
 125
 126         return dwmci_probe(dev);
 127 }
 128
 129 static int socfpga_dwmmc_bind(struct udevice *dev)
 130 {
 131 #ifdef CONFIG_BLK
 132         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 133         int ret;
 134
 135         ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 136         if (ret)
 137                 return ret;
 138 #endif
 139
 140         return 0;
 141 }
 142
 143 static const struct udevice_id socfpga_dwmmc_ids[] = {
 144         { .compatible = "altr,socfpga-dw-mshc" },
 145         { }
 146 };
 147
 148 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
 149         .name           = "socfpga_dwmmc",
 150         .id             = UCLASS_MMC,
 151         .of_match       = socfpga_dwmmc_ids,
 152         .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
 153         .ops            = &dm_dwmci_ops,
 154         .bind           = socfpga_dwmmc_bind,
 155         .probe          = socfpga_dwmmc_probe,
 156         .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
 157         .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
 158 };