git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/zynq_nand.c

   1 /*
   2  * (C) Copyright 2016 Xilinx, Inc.
   3  *
   4  * Xilinx Zynq NAND Flash Controller Driver
   5  * This driver is based on plat_nand.c and mxc_nand.c drivers
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <linux/errno.h>
  14 #include <nand.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/rawnand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/mtd/nand_ecc.h>
  19 #include <asm/arch/hardware.h>
  20
  21 /* The NAND flash driver defines */
  22 #define ZYNQ_NAND_CMD_PHASE             1
  23 #define ZYNQ_NAND_DATA_PHASE            2
  24 #define ZYNQ_NAND_ECC_SIZE              512
  25 #define ZYNQ_NAND_SET_OPMODE_8BIT       (0 << 0)
  26 #define ZYNQ_NAND_SET_OPMODE_16BIT      (1 << 0)
  27 #define ZYNQ_NAND_ECC_STATUS            (1 << 6)
  28 #define ZYNQ_MEMC_CLRCR_INT_CLR1        (1 << 4)
  29 #define ZYNQ_MEMC_SR_RAW_INT_ST1        (1 << 6)
  30 #define ZYNQ_MEMC_SR_INT_ST1            (1 << 4)
  31 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK    0xC
  32
  33 /* Flash memory controller operating parameters */
  34 #define ZYNQ_NAND_CLR_CONFIG    ((0x1 << 1)  |  /* Disable interrupt */ \
  35                                 (0x1 << 4)   |  /* Clear interrupt */ \
  36                                 (0x1 << 6))     /* Disable ECC interrupt */
  37
  38 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  39
  40 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  41 #define ZYNQ_NAND_SET_CYCLES    ((0x2 << 20) |  /* t_rr from nand_cycles */ \
  42                                 (0x2 << 17)  |  /* t_ar from nand_cycles */ \
  43                                 (0x1 << 14)  |  /* t_clr from nand_cycles */ \
  44                                 (0x3 << 11)  |  /* t_wp from nand_cycles */ \
  45                                 (0x2 << 8)   |  /* t_rea from nand_cycles */ \
  46                                 (0x5 << 4)   |  /* t_wc from nand_cycles */ \
  47                                 (0x5 << 0))     /* t_rc from nand_cycles */
  48 #endif
  49
  50
  51 #define ZYNQ_NAND_DIRECT_CMD    ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
  52                                 (0x2 << 21))    /* UpdateRegs operation */
  53
  54 #define ZYNQ_NAND_ECC_CONFIG    ((0x1 << 2)  |  /* ECC available on APB */ \
  55                                 (0x1 << 4)   |  /* ECC read at end of page */ \
  56                                 (0x0 << 5))     /* No Jumping */
  57
  58 #define ZYNQ_NAND_ECC_CMD1      ((0x80)      |  /* Write command */ \
  59                                 (0x00 << 8)  |  /* Read command */ \
  60                                 (0x30 << 16) |  /* Read End command */ \
  61                                 (0x1 << 24))    /* Read End command calid */
  62
  63 #define ZYNQ_NAND_ECC_CMD2      ((0x85)      |  /* Write col change cmd */ \
  64                                 (0x05 << 8)  |  /* Read col change cmd */ \
  65                                 (0xE0 << 16) |  /* Read col change end cmd */ \
  66                                 (0x1 << 24))    /* Read col change
  67                                                         end cmd valid */
  68 /* AXI Address definitions */
  69 #define START_CMD_SHIFT                 3
  70 #define END_CMD_SHIFT                   11
  71 #define END_CMD_VALID_SHIFT             20
  72 #define ADDR_CYCLES_SHIFT               21
  73 #define CLEAR_CS_SHIFT                  21
  74 #define ECC_LAST_SHIFT                  10
  75 #define COMMAND_PHASE                   (0 << 19)
  76 #define DATA_PHASE                      (1 << 19)
  77 #define ONDIE_ECC_FEATURE_ADDR          0x90
  78 #define ONDIE_ECC_FEATURE_ENABLE        0x08
  79
  80 #define ZYNQ_NAND_ECC_LAST      (1 << ECC_LAST_SHIFT)   /* Set ECC_Last */
  81 #define ZYNQ_NAND_CLEAR_CS      (1 << CLEAR_CS_SHIFT)   /* Clear chip select */
  82
  83 /* ECC block registers bit position and bit mask */
  84 #define ZYNQ_NAND_ECC_BUSY      (1 << 6)        /* ECC block is busy */
  85 #define ZYNQ_NAND_ECC_MASK      0x00FFFFFF      /* ECC value mask */
  86
  87 #ifndef NAND_CMD_LOCK_TIGHT
  88 #define NAND_CMD_LOCK_TIGHT 0x2c
  89 #endif
  90
  91 #ifndef NAND_CMD_LOCK_STATUS
  92 #define NAND_CMD_LOCK_STATUS 0x7a
  93 #endif
  94
  95 /* SMC register set */
  96 struct zynq_nand_smc_regs {
  97         u32 csr;                /* 0x00 */
  98         u32 reserved0[2];
  99         u32 cfr;                /* 0x0C */
 100         u32 dcr;                /* 0x10 */
 101         u32 scr;                /* 0x14 */
 102         u32 sor;                /* 0x18 */
 103         u32 reserved1[249];
 104         u32 esr;                /* 0x400 */
 105         u32 emcr;               /* 0x404 */
 106         u32 emcmd1r;            /* 0x408 */
 107         u32 emcmd2r;            /* 0x40C */
 108         u32 reserved2[2];
 109         u32 eval0r;             /* 0x418 */
 110 };
 111 #define zynq_nand_smc_base      ((struct zynq_nand_smc_regs __iomem *)\
 112                                 ZYNQ_SMC_BASEADDR)
 113
 114 /*
 115  * struct zynq_nand_info - Defines the NAND flash driver instance
 116  * @parts:              Pointer to the mtd_partition structure
 117  * @nand_base:          Virtual address of the NAND flash device
 118  * @end_cmd_pending:    End command is pending
 119  * @end_cmd:            End command
 120  */
 121 struct zynq_nand_info {
 122         void __iomem    *nand_base;
 123         u8              end_cmd_pending;
 124         u8              end_cmd;
 125 };
 126
 127 /*
 128  * struct zynq_nand_command_format - Defines NAND flash command format
 129  * @start_cmd:          First cycle command (Start command)
 130  * @end_cmd:            Second cycle command (Last command)
 131  * @addr_cycles:        Number of address cycles required to send the address
 132  * @end_cmd_valid:      The second cycle command is valid for cmd or data phase
 133  */
 134 struct zynq_nand_command_format {
 135         u8 start_cmd;
 136         u8 end_cmd;
 137         u8 addr_cycles;
 138         u8 end_cmd_valid;
 139 };
 140
 141 /*  The NAND flash operations command format */
 142 static const struct zynq_nand_command_format zynq_nand_commands[] = {
 143         {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
 144         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
 145         {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
 146         {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
 147         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
 148         {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
 149         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
 150         {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
 151         {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 152         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 153         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
 154         {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
 155         {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
 156         {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
 157         {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
 158         {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
 159         {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 160         /* Add all the flash commands supported by the flash device */
 161 };
 162
 163 /* Define default oob placement schemes for large and small page devices */
 164 static struct nand_ecclayout nand_oob_16 = {
 165         .eccbytes = 3,
 166         .eccpos = {0, 1, 2},
 167         .oobfree = {
 168                 { .offset = 8, .length = 8 }
 169         }
 170 };
 171
 172 static struct nand_ecclayout nand_oob_64 = {
 173         .eccbytes = 12,
 174         .eccpos = {
 175                    52, 53, 54, 55, 56, 57,
 176                    58, 59, 60, 61, 62, 63},
 177         .oobfree = {
 178                 { .offset = 2, .length = 50 }
 179         }
 180 };
 181
 182 static struct nand_ecclayout ondie_nand_oob_64 = {
 183         .eccbytes = 32,
 184
 185         .eccpos = {
 186                 8, 9, 10, 11, 12, 13, 14, 15,
 187                 24, 25, 26, 27, 28, 29, 30, 31,
 188                 40, 41, 42, 43, 44, 45, 46, 47,
 189                 56, 57, 58, 59, 60, 61, 62, 63
 190         },
 191
 192         .oobfree = {
 193                 { .offset = 4, .length = 4 },
 194                 { .offset = 20, .length = 4 },
 195                 { .offset = 36, .length = 4 },
 196                 { .offset = 52, .length = 4 }
 197         }
 198 };
 199
 200 /* bbt decriptors for chips with on-die ECC and
 201    chips with 64-byte OOB */
 202 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 203 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 204
 205 static struct nand_bbt_descr bbt_main_descr = {
 206         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 207                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 208         .offs = 4,
 209         .len = 4,
 210         .veroffs = 20,
 211         .maxblocks = 4,
 212         .pattern = bbt_pattern
 213 };
 214
 215 static struct nand_bbt_descr bbt_mirror_descr = {
 216         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 217                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 218         .offs = 4,
 219         .len = 4,
 220         .veroffs = 20,
 221         .maxblocks = 4,
 222         .pattern = mirror_pattern
 223 };
 224
 225 /*
 226  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
 227  *
 228  * returns: status for command completion, -1 for Timeout
 229  */
 230 static int zynq_nand_waitfor_ecc_completion(void)
 231 {
 232         unsigned long timeout;
 233         u32 status;
 234
 235         /* Wait max 10us */
 236         timeout = 10;
 237         status = readl(&zynq_nand_smc_base->esr);
 238         while (status & ZYNQ_NAND_ECC_BUSY) {
 239                 status = readl(&zynq_nand_smc_base->esr);
 240                 if (timeout == 0)
 241                         return -1;
 242                 timeout--;
 243                 udelay(1);
 244         }
 245
 246         return status;
 247 }
 248
 249 /*
 250  * zynq_nand_init_nand_flash - Initialize NAND controller
 251  * @option:     Device property flags
 252  *
 253  * This function initializes the NAND flash interface on the NAND controller.
 254  *
 255  * returns:     0 on success or error value on failure
 256  */
 257 static int zynq_nand_init_nand_flash(int option)
 258 {
 259         u32 status;
 260
 261         /* disable interrupts */
 262         writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
 263 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 264         /* Initialize the NAND interface by setting cycles and operation mode */
 265         writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
 266 #endif
 267         if (option & NAND_BUSWIDTH_16)
 268                 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
 269         else
 270                 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
 271
 272         writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
 273
 274         /* Wait till the ECC operation is complete */
 275         status = zynq_nand_waitfor_ecc_completion();
 276         if (status < 0) {
 277                 printf("%s: Timeout\n", __func__);
 278                 return status;
 279         }
 280
 281         /* Set the command1 and command2 register */
 282         writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
 283         writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
 284
 285         return 0;
 286 }
 287
 288 /*
 289  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
 290  * @mtd:        Pointer to the mtd_info structure
 291  * @data:       Pointer to the page data
 292  * @ecc_code:   Pointer to the ECC buffer where ECC data needs to be stored
 293  *
 294  * This function retrieves the Hardware ECC data from the controller and returns
 295  * ECC data back to the MTD subsystem.
 296  *
 297  * returns:     0 on success or error value on failure
 298  */
 299 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 300                 u8 *ecc_code)
 301 {
 302         u32 ecc_value = 0;
 303         u8 ecc_reg, ecc_byte;
 304         u32 ecc_status;
 305
 306         /* Wait till the ECC operation is complete */
 307         ecc_status = zynq_nand_waitfor_ecc_completion();
 308         if (ecc_status < 0) {
 309                 printf("%s: Timeout\n", __func__);
 310                 return ecc_status;
 311         }
 312
 313         for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 314                 /* Read ECC value for each block */
 315                 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
 316
 317                 /* Get the ecc status from ecc read value */
 318                 ecc_status = (ecc_value >> 24) & 0xFF;
 319
 320                 /* ECC value valid */
 321                 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
 322                         for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
 323                                 /* Copy ECC bytes to MTD buffer */
 324                                 *ecc_code = ecc_value & 0xFF;
 325                                 ecc_value = ecc_value >> 8;
 326                                 ecc_code++;
 327                         }
 328                 } else {
 329                         debug("%s: ecc status failed\n", __func__);
 330                 }
 331         }
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * onehot - onehot function
 338  * @value:      value to check for onehot
 339  *
 340  * This function checks whether a value is onehot or not.
 341  * onehot is if and only if one bit is set.
 342  *
 343  * FIXME: Try to move this in common.h
 344  */
 345 static bool onehot(unsigned short value)
 346 {
 347         bool onehot;
 348
 349         onehot = value && !(value & (value - 1));
 350         return onehot;
 351 }
 352
 353 /*
 354  * zynq_nand_correct_data - ECC correction function
 355  * @mtd:        Pointer to the mtd_info structure
 356  * @buf:        Pointer to the page data
 357  * @read_ecc:   Pointer to the ECC value read from spare data area
 358  * @calc_ecc:   Pointer to the calculated ECC value
 359  *
 360  * This function corrects the ECC single bit errors & detects 2-bit errors.
 361  *
 362  * returns:     0 if no ECC errors found
 363  *              1 if single bit error found and corrected.
 364  *              -1 if multiple ECC errors found.
 365  */
 366 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
 367                         unsigned char *read_ecc, unsigned char *calc_ecc)
 368 {
 369         unsigned char bit_addr;
 370         unsigned int byte_addr;
 371         unsigned short ecc_odd, ecc_even;
 372         unsigned short read_ecc_lower, read_ecc_upper;
 373         unsigned short calc_ecc_lower, calc_ecc_upper;
 374
 375         read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
 376         read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
 377
 378         calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
 379         calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
 380
 381         ecc_odd = read_ecc_lower ^ calc_ecc_lower;
 382         ecc_even = read_ecc_upper ^ calc_ecc_upper;
 383
 384         if ((ecc_odd == 0) && (ecc_even == 0))
 385                 return 0;       /* no error */
 386
 387         if (ecc_odd == (~ecc_even & 0xfff)) {
 388                 /* bits [11:3] of error code is byte offset */
 389                 byte_addr = (ecc_odd >> 3) & 0x1ff;
 390                 /* bits [2:0] of error code is bit offset */
 391                 bit_addr = ecc_odd & 0x7;
 392                 /* Toggling error bit */
 393                 buf[byte_addr] ^= (1 << bit_addr);
 394                 return 1;
 395         }
 396
 397         if (onehot(ecc_odd | ecc_even))
 398                 return 1; /* one error in parity */
 399
 400         return -1; /* Uncorrectable error */
 401 }
 402
 403 /*
 404  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
 405  * @mtd:        mtd info structure
 406  * @chip:       nand chip info structure
 407  * @page:       page number to read
 408  * @sndcmd:     flag whether to issue read command or not
 409  */
 410 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 411                         int page)
 412 {
 413         unsigned long data_phase_addr = 0;
 414         int data_width = 4;
 415         u8 *p;
 416
 417         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 418
 419         p = chip->oob_poi;
 420         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 421         p += mtd->oobsize - data_width;
 422
 423         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 424         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 425         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 426         chip->read_buf(mtd, p, data_width);
 427
 428         return 0;
 429 }
 430
 431 /*
 432  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
 433  * @mtd:        mtd info structure
 434  * @chip:       nand chip info structure
 435  * @page:       page number to write
 436  */
 437 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 438                              int page)
 439 {
 440         int status = 0, data_width = 4;
 441         const u8 *buf = chip->oob_poi;
 442         unsigned long data_phase_addr = 0;
 443
 444         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 445
 446         chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
 447         buf += mtd->oobsize - data_width;
 448
 449         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 450         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 451         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 452         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 453         chip->write_buf(mtd, buf, data_width);
 454
 455         /* Send command to program the OOB data */
 456         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 457         status = chip->waitfunc(mtd, chip);
 458
 459         return status & NAND_STATUS_FAIL ? -EIO : 0;
 460 }
 461
 462 /*
 463  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
 464  * @mtd:        mtd info structure
 465  * @chip:       nand chip info structure
 466  * @buf:        buffer to store read data
 467  * @oob_required: must write chip->oob_poi to OOB
 468  * @page:       page number to read
 469  */
 470 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 471                                    u8 *buf,  int oob_required, int page)
 472 {
 473         unsigned long data_width = 4;
 474         unsigned long data_phase_addr = 0;
 475         u8 *p;
 476
 477         chip->read_buf(mtd, buf, mtd->writesize);
 478
 479         p = chip->oob_poi;
 480         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 481         p += (mtd->oobsize - data_width);
 482
 483         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 484         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 485         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 486
 487         chip->read_buf(mtd, p, data_width);
 488         return 0;
 489 }
 490
 491 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
 492                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 493 {
 494         chip->read_buf(mtd, buf, mtd->writesize);
 495         return 0;
 496 }
 497
 498 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
 499                                     struct nand_chip *chip, u32 data_offs,
 500                                     u32 readlen, u8 *buf, int page)
 501 {
 502         if (data_offs != 0) {
 503                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
 504                 buf += data_offs;
 505         }
 506         chip->read_buf(mtd, buf, readlen);
 507
 508         return 0;
 509 }
 510
 511 /*
 512  * zynq_nand_write_page_raw - [Intern] raw page write function
 513  * @mtd:        mtd info structure
 514  * @chip:       nand chip info structure
 515  * @buf:        data buffer
 516  * @oob_required: must write chip->oob_poi to OOB
 517  */
 518 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
 519         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 520 {
 521         unsigned long data_width = 4;
 522         unsigned long data_phase_addr = 0;
 523         u8 *p;
 524
 525         chip->write_buf(mtd, buf, mtd->writesize);
 526
 527         p = chip->oob_poi;
 528         chip->write_buf(mtd, p, (mtd->oobsize - data_width));
 529         p += (mtd->oobsize - data_width);
 530
 531         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 532         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 533         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 534         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 535
 536         chip->write_buf(mtd, p, data_width);
 537
 538         return 0;
 539 }
 540
 541 /*
 542  * nand_write_page_hwecc - Hardware ECC based page write function
 543  * @mtd:        Pointer to the mtd info structure
 544  * @chip:       Pointer to the NAND chip info structure
 545  * @buf:        Pointer to the data buffer
 546  * @oob_required: must write chip->oob_poi to OOB
 547  *
 548  * This functions writes data and hardware generated ECC values in to the page.
 549  */
 550 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
 551         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 552 {
 553         int i, eccsteps, eccsize = chip->ecc.size;
 554         u8 *ecc_calc = chip->buffers->ecccalc;
 555         const u8 *p = buf;
 556         u32 *eccpos = chip->ecc.layout->eccpos;
 557         unsigned long data_phase_addr = 0;
 558         unsigned long data_width = 4;
 559         u8 *oob_ptr;
 560
 561         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 562                 chip->write_buf(mtd, p, eccsize);
 563                 p += eccsize;
 564         }
 565         chip->write_buf(mtd, p, (eccsize - data_width));
 566         p += eccsize - data_width;
 567
 568         /* Set ECC Last bit to 1 */
 569         data_phase_addr = (unsigned long) chip->IO_ADDR_W;
 570         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 571         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 572         chip->write_buf(mtd, p, data_width);
 573
 574         /* Wait for ECC to be calculated and read the error values */
 575         p = buf;
 576         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 577
 578         for (i = 0; i < chip->ecc.total; i++)
 579                 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
 580
 581         /* Clear ECC last bit */
 582         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 583         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 584         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 585
 586         /* Write the spare area with ECC bytes */
 587         oob_ptr = chip->oob_poi;
 588         chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 589
 590         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 591         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 592         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 593         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 594         oob_ptr += (mtd->oobsize - data_width);
 595         chip->write_buf(mtd, oob_ptr, data_width);
 596
 597         return 0;
 598 }
 599
 600 /*
 601  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
 602  * write function
 603  * @mtd:        mtd info structure
 604  * @chip:       nand chip info structure
 605  * @buf:        data buffer
 606  * @oob_required: must write chip->oob_poi to OOB
 607  */
 608 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
 609         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 610 {
 611         int i, eccsize = chip->ecc.size;
 612         int eccbytes = chip->ecc.bytes;
 613         int eccsteps = chip->ecc.steps;
 614         u8 *ecc_calc = chip->buffers->ecccalc;
 615         const u8 *p = buf;
 616         u32 *eccpos = chip->ecc.layout->eccpos;
 617
 618         /* Software ecc calculation */
 619         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 620                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 621
 622         for (i = 0; i < chip->ecc.total; i++)
 623                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
 624
 625         return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 626 }
 627
 628 /*
 629  * nand_read_page_hwecc - Hardware ECC based page read function
 630  * @mtd:        Pointer to the mtd info structure
 631  * @chip:       Pointer to the NAND chip info structure
 632  * @buf:        Pointer to the buffer to store read data
 633  * @oob_required: must write chip->oob_poi to OOB
 634  * @page:       page number to read
 635  *
 636  * This functions reads data and checks the data integrity by comparing hardware
 637  * generated ECC values and read ECC values from spare area.
 638  *
 639  * returns:     0 always and updates ECC operation status in to MTD structure
 640  */
 641 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
 642         struct nand_chip *chip, u8 *buf, int oob_required, int page)
 643 {
 644         int i, stat, eccsteps, eccsize = chip->ecc.size;
 645         int eccbytes = chip->ecc.bytes;
 646         u8 *p = buf;
 647         u8 *ecc_calc = chip->buffers->ecccalc;
 648         u8 *ecc_code = chip->buffers->ecccode;
 649         u32 *eccpos = chip->ecc.layout->eccpos;
 650         unsigned long data_phase_addr = 0;
 651         unsigned long data_width = 4;
 652         u8 *oob_ptr;
 653
 654         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 655                 chip->read_buf(mtd, p, eccsize);
 656                 p += eccsize;
 657         }
 658         chip->read_buf(mtd, p, (eccsize - data_width));
 659         p += eccsize - data_width;
 660
 661         /* Set ECC Last bit to 1 */
 662         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 663         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 664         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 665         chip->read_buf(mtd, p, data_width);
 666
 667         /* Read the calculated ECC value */
 668         p = buf;
 669         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 670
 671         /* Clear ECC last bit */
 672         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 673         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 674         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 675
 676         /* Read the stored ECC value */
 677         oob_ptr = chip->oob_poi;
 678         chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 679
 680         /* de-assert chip select */
 681         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 682         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 683         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 684
 685         oob_ptr += (mtd->oobsize - data_width);
 686         chip->read_buf(mtd, oob_ptr, data_width);
 687
 688         for (i = 0; i < chip->ecc.total; i++)
 689                 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
 690
 691         eccsteps = chip->ecc.steps;
 692         p = buf;
 693
 694         /* Check ECC error for all blocks and correct if it is correctable */
 695         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 696                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 697                 if (stat < 0)
 698                         mtd->ecc_stats.failed++;
 699                 else
 700                         mtd->ecc_stats.corrected += stat;
 701         }
 702         return 0;
 703 }
 704
 705 /*
 706  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
 707  * read function
 708  * @mtd:        mtd info structure
 709  * @chip:       nand chip info structure
 710  * @buf:        buffer to store read data
 711  * @page:       page number to read
 712  */
 713 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
 714         struct nand_chip *chip, u8 *buf, int oob_required,  int page)
 715 {
 716         int i, eccsize = chip->ecc.size;
 717         int eccbytes = chip->ecc.bytes;
 718         int eccsteps = chip->ecc.steps;
 719         u8 *p = buf;
 720         u8 *ecc_calc = chip->buffers->ecccalc;
 721         u8 *ecc_code = chip->buffers->ecccode;
 722         u32 *eccpos = chip->ecc.layout->eccpos;
 723
 724         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 725
 726         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 727                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 728
 729         for (i = 0; i < chip->ecc.total; i++)
 730                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 731
 732         eccsteps = chip->ecc.steps;
 733         p = buf;
 734
 735         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 736                 int stat;
 737
 738                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 739                 if (stat < 0)
 740                         mtd->ecc_stats.failed++;
 741                 else
 742                         mtd->ecc_stats.corrected += stat;
 743         }
 744         return 0;
 745 }
 746
 747 /*
 748  * zynq_nand_select_chip - Select the flash device
 749  * @mtd:        Pointer to the mtd_info structure
 750  * @chip:       Chip number to be selected
 751  *
 752  * This function is empty as the NAND controller handles chip select line
 753  * internally based on the chip address passed in command and data phase.
 754  */
 755 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 756 {
 757         /* Not support multiple chips yet */
 758 }
 759
 760 /*
 761  * zynq_nand_cmd_function - Send command to NAND device
 762  * @mtd:        Pointer to the mtd_info structure
 763  * @command:    The command to be sent to the flash device
 764  * @column:     The column address for this command, -1 if none
 765  * @page_addr:  The page address for this command, -1 if none
 766  */
 767 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 768                                  int column, int page_addr)
 769 {
 770         struct nand_chip *chip = mtd->priv;
 771         const struct zynq_nand_command_format *curr_cmd = NULL;
 772         struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
 773         void *cmd_addr;
 774         unsigned long cmd_data = 0;
 775         unsigned long cmd_phase_addr = 0;
 776         unsigned long data_phase_addr = 0;
 777         u8 end_cmd = 0;
 778         u8 end_cmd_valid = 0;
 779         u32 index;
 780
 781         if (xnand->end_cmd_pending) {
 782                 /* Check for end command if this command request is same as the
 783                  * pending command then return
 784                  */
 785                 if (xnand->end_cmd == command) {
 786                         xnand->end_cmd = 0;
 787                         xnand->end_cmd_pending = 0;
 788                         return;
 789                 }
 790         }
 791
 792         /* Emulate NAND_CMD_READOOB for large page device */
 793         if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
 794             (command == NAND_CMD_READOOB)) {
 795                 column += mtd->writesize;
 796                 command = NAND_CMD_READ0;
 797         }
 798
 799         /* Get the command format */
 800         for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
 801                 if (command == zynq_nand_commands[index].start_cmd)
 802                         break;
 803
 804         if (index == ARRAY_SIZE(zynq_nand_commands)) {
 805                 printf("%s: Unsupported start cmd %02x\n", __func__, command);
 806                 return;
 807         }
 808         curr_cmd = &zynq_nand_commands[index];
 809
 810         /* Clear interrupt */
 811         writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
 812
 813         /* Get the command phase address */
 814         if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 815                 end_cmd_valid = 1;
 816
 817         if (curr_cmd->end_cmd == NAND_CMD_NONE)
 818                 end_cmd = 0x0;
 819         else
 820                 end_cmd = curr_cmd->end_cmd;
 821
 822         cmd_phase_addr = (unsigned long)xnand->nand_base        |
 823                         (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT)    |
 824                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 825                         (COMMAND_PHASE)                                 |
 826                         (end_cmd << END_CMD_SHIFT)                      |
 827                         (curr_cmd->start_cmd << START_CMD_SHIFT);
 828
 829         cmd_addr = (void __iomem *)cmd_phase_addr;
 830
 831         /* Get the data phase address */
 832         end_cmd_valid = 0;
 833
 834         data_phase_addr = (unsigned long)xnand->nand_base       |
 835                         (0x0 << CLEAR_CS_SHIFT)                         |
 836                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 837                         (DATA_PHASE)                                    |
 838                         (end_cmd << END_CMD_SHIFT)                      |
 839                         (0x0 << ECC_LAST_SHIFT);
 840
 841         chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
 842         chip->IO_ADDR_W = chip->IO_ADDR_R;
 843
 844         /* Command phase AXI Read & Write */
 845         if (column != -1 && page_addr != -1) {
 846                 /* Adjust columns for 16 bit bus width */
 847                 if (chip->options & NAND_BUSWIDTH_16)
 848                         column >>= 1;
 849                 cmd_data = column;
 850                 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
 851                         cmd_data |= page_addr << 16;
 852                         /* Another address cycle for devices > 128MiB */
 853                         if (chip->chipsize > (128 << 20)) {
 854                                 writel(cmd_data, cmd_addr);
 855                                 cmd_data = (page_addr >> 16);
 856                         }
 857                 } else {
 858                         cmd_data |= page_addr << 8;
 859                 }
 860         } else if (page_addr != -1)  { /* Erase */
 861                 cmd_data = page_addr;
 862         } else if (column != -1) { /* Change read/write column, read id etc */
 863                 /* Adjust columns for 16 bit bus width */
 864                 if ((chip->options & NAND_BUSWIDTH_16) &&
 865                     ((command == NAND_CMD_READ0) ||
 866                      (command == NAND_CMD_SEQIN) ||
 867                      (command == NAND_CMD_RNDOUT) ||
 868                      (command == NAND_CMD_RNDIN)))
 869                         column >>= 1;
 870                 cmd_data = column;
 871         }
 872
 873         writel(cmd_data, cmd_addr);
 874
 875         if (curr_cmd->end_cmd_valid) {
 876                 xnand->end_cmd = curr_cmd->end_cmd;
 877                 xnand->end_cmd_pending = 1;
 878         }
 879
 880         ndelay(100);
 881
 882         if ((command == NAND_CMD_READ0) ||
 883             (command == NAND_CMD_RESET) ||
 884             (command == NAND_CMD_PARAM) ||
 885             (command == NAND_CMD_GET_FEATURES))
 886                 /* wait until command is processed */
 887                 nand_wait_ready(mtd);
 888 }
 889
 890 /*
 891  * zynq_nand_read_buf - read chip data into buffer
 892  * @mtd:        MTD device structure
 893  * @buf:        buffer to store date
 894  * @len:        number of bytes to read
 895  */
 896 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 897 {
 898         struct nand_chip *chip = mtd->priv;
 899
 900         /* Make sure that buf is 32 bit aligned */
 901         if (((unsigned long)buf & 0x3) != 0) {
 902                 if (((unsigned long)buf & 0x1) != 0) {
 903                         if (len) {
 904                                 *buf = readb(chip->IO_ADDR_R);
 905                                 buf += 1;
 906                                 len--;
 907                         }
 908                 }
 909
 910                 if (((unsigned long)buf & 0x3) != 0) {
 911                         if (len >= 2) {
 912                                 *(u16 *)buf = readw(chip->IO_ADDR_R);
 913                                 buf += 2;
 914                                 len -= 2;
 915                         }
 916                 }
 917         }
 918
 919         /* copy aligned data */
 920         while (len >= 4) {
 921                 *(u32 *)buf = readl(chip->IO_ADDR_R);
 922                 buf += 4;
 923                 len -= 4;
 924         }
 925
 926         /* mop up any remaining bytes */
 927         if (len) {
 928                 if (len >= 2) {
 929                         *(u16 *)buf = readw(chip->IO_ADDR_R);
 930                         buf += 2;
 931                         len -= 2;
 932                 }
 933                 if (len)
 934                         *buf = readb(chip->IO_ADDR_R);
 935         }
 936 }
 937
 938 /*
 939  * zynq_nand_write_buf - write buffer to chip
 940  * @mtd:        MTD device structure
 941  * @buf:        data buffer
 942  * @len:        number of bytes to write
 943  */
 944 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 945 {
 946         struct nand_chip *chip = mtd->priv;
 947         const u32 *nand = chip->IO_ADDR_W;
 948
 949         /* Make sure that buf is 32 bit aligned */
 950         if (((unsigned long)buf & 0x3) != 0) {
 951                 if (((unsigned long)buf & 0x1) != 0) {
 952                         if (len) {
 953                                 writeb(*buf, nand);
 954                                 buf += 1;
 955                                 len--;
 956                         }
 957                 }
 958
 959                 if (((unsigned long)buf & 0x3) != 0) {
 960                         if (len >= 2) {
 961                                 writew(*(u16 *)buf, nand);
 962                                 buf += 2;
 963                                 len -= 2;
 964                         }
 965                 }
 966         }
 967
 968         /* copy aligned data */
 969         while (len >= 4) {
 970                 writel(*(u32 *)buf, nand);
 971                 buf += 4;
 972                 len -= 4;
 973         }
 974
 975         /* mop up any remaining bytes */
 976         if (len) {
 977                 if (len >= 2) {
 978                         writew(*(u16 *)buf, nand);
 979                         buf += 2;
 980                         len -= 2;
 981                 }
 982
 983                 if (len)
 984                         writeb(*buf, nand);
 985         }
 986 }
 987
 988 /*
 989  * zynq_nand_device_ready - Check device ready/busy line
 990  * @mtd:        Pointer to the mtd_info structure
 991  *
 992  * returns:     0 on busy or 1 on ready state
 993  */
 994 static int zynq_nand_device_ready(struct mtd_info *mtd)
 995 {
 996         u32 csr_val;
 997
 998         csr_val = readl(&zynq_nand_smc_base->csr);
 999         /* Check the raw_int_status1 bit */
1000         if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1001                 /* Clear the interrupt condition */
1002                 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
1003                 return 1;
1004         }
1005
1006         return 0;
1007 }
1008
1009 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
1010 {
1011         struct zynq_nand_info *xnand;
1012         struct mtd_info *mtd;
1013         unsigned long ecc_page_size;
1014         u8 maf_id, dev_id, i;
1015         u8 get_feature[4];
1016         u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1017         unsigned long ecc_cfg;
1018         int ondie_ecc_enabled = 0;
1019         int err = -1;
1020
1021         xnand = calloc(1, sizeof(struct zynq_nand_info));
1022         if (!xnand) {
1023                 printf("%s: failed to allocate\n", __func__);
1024                 goto fail;
1025         }
1026
1027         xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1028         mtd = nand_to_mtd(nand_chip);
1029
1030         nand_chip->priv = xnand;
1031         mtd->priv = nand_chip;
1032
1033         /* Set address of NAND IO lines */
1034         nand_chip->IO_ADDR_R = xnand->nand_base;
1035         nand_chip->IO_ADDR_W = xnand->nand_base;
1036
1037         /* Set the driver entry points for MTD */
1038         nand_chip->cmdfunc = zynq_nand_cmd_function;
1039         nand_chip->dev_ready = zynq_nand_device_ready;
1040         nand_chip->select_chip = zynq_nand_select_chip;
1041
1042         /* If we don't set this delay driver sets 20us by default */
1043         nand_chip->chip_delay = 30;
1044
1045         /* Buffer read/write routines */
1046         nand_chip->read_buf = zynq_nand_read_buf;
1047         nand_chip->write_buf = zynq_nand_write_buf;
1048
1049         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1050
1051         /* Initialize the NAND flash interface on NAND controller */
1052         if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1053                 printf("%s: nand flash init failed\n", __func__);
1054                 goto fail;
1055         }
1056
1057         /* first scan to find the device and get the page size */
1058         if (nand_scan_ident(mtd, 1, NULL)) {
1059                 printf("%s: nand_scan_ident failed\n", __func__);
1060                 goto fail;
1061         }
1062         /* Send the command for reading device ID */
1063         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1064         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1065
1066         /* Read manufacturer and device IDs */
1067         maf_id = nand_chip->read_byte(mtd);
1068         dev_id = nand_chip->read_byte(mtd);
1069
1070         if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1071                                  (dev_id == 0xa1) || (dev_id == 0xb1) ||
1072                                  (dev_id == 0xaa) || (dev_id == 0xba) ||
1073                                  (dev_id == 0xda) || (dev_id == 0xca) ||
1074                                  (dev_id == 0xac) || (dev_id == 0xbc) ||
1075                                  (dev_id == 0xdc) || (dev_id == 0xcc) ||
1076                                  (dev_id == 0xa3) || (dev_id == 0xb3) ||
1077                                  (dev_id == 0xd3) || (dev_id == 0xc3))) {
1078                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1079                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1080                 for (i = 0; i < 4; i++)
1081                         writeb(set_feature[i], nand_chip->IO_ADDR_W);
1082
1083                 /* Wait for 1us after writing data with SET_FEATURES command */
1084                 ndelay(1000);
1085
1086                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1087                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1088                 nand_chip->read_buf(mtd, get_feature, 4);
1089
1090                 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1091                         debug("%s: OnDie ECC flash\n", __func__);
1092                         ondie_ecc_enabled = 1;
1093                 } else {
1094                         printf("%s: Unable to detect OnDie ECC\n", __func__);
1095                 }
1096         }
1097
1098         if (ondie_ecc_enabled) {
1099                 /* Bypass the controller ECC block */
1100                 ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1101                 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1102                 writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1103
1104                 /* The software ECC routines won't work
1105                  * with the SMC controller
1106                  */
1107                 nand_chip->ecc.mode = NAND_ECC_HW;
1108                 nand_chip->ecc.strength = 1;
1109                 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1110                 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1111                 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1112                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1113                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1114                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1115                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1116                 nand_chip->ecc.size = mtd->writesize;
1117                 nand_chip->ecc.bytes = 0;
1118
1119                 /* NAND with on-die ECC supports subpage reads */
1120                 nand_chip->options |= NAND_SUBPAGE_READ;
1121
1122                 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1123                 if (ondie_ecc_enabled) {
1124                         nand_chip->ecc.layout = &ondie_nand_oob_64;
1125                         /* Use the BBT pattern descriptors */
1126                         nand_chip->bbt_td = &bbt_main_descr;
1127                         nand_chip->bbt_md = &bbt_mirror_descr;
1128                 }
1129         } else {
1130                 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1131                 nand_chip->ecc.mode = NAND_ECC_HW;
1132                 nand_chip->ecc.strength = 1;
1133                 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1134                 nand_chip->ecc.bytes = 3;
1135                 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1136                 nand_chip->ecc.correct = zynq_nand_correct_data;
1137                 nand_chip->ecc.hwctl = NULL;
1138                 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1139                 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1140                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1141                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1142                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1143                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1144
1145                 switch (mtd->writesize) {
1146                 case 512:
1147                         ecc_page_size = 0x1;
1148                         /* Set the ECC memory config register */
1149                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1150                                &zynq_nand_smc_base->emcr);
1151                         break;
1152                 case 1024:
1153                         ecc_page_size = 0x2;
1154                         /* Set the ECC memory config register */
1155                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1156                                &zynq_nand_smc_base->emcr);
1157                         break;
1158                 case 2048:
1159                         ecc_page_size = 0x3;
1160                         /* Set the ECC memory config register */
1161                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1162                                &zynq_nand_smc_base->emcr);
1163                         break;
1164                 default:
1165                         nand_chip->ecc.mode = NAND_ECC_SOFT;
1166                         nand_chip->ecc.calculate = nand_calculate_ecc;
1167                         nand_chip->ecc.correct = nand_correct_data;
1168                         nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1169                         nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1170                         nand_chip->ecc.size = 256;
1171                         break;
1172                 }
1173
1174                 if (mtd->oobsize == 16)
1175                         nand_chip->ecc.layout = &nand_oob_16;
1176                 else if (mtd->oobsize == 64)
1177                         nand_chip->ecc.layout = &nand_oob_64;
1178                 else
1179                         printf("%s: No oob layout found\n", __func__);
1180         }
1181
1182         /* Second phase scan */
1183         if (nand_scan_tail(mtd)) {
1184                 printf("%s: nand_scan_tail failed\n", __func__);
1185                 goto fail;
1186         }
1187         if (nand_register(devnum, mtd))
1188                 goto fail;
1189         return 0;
1190 fail:
1191         free(xnand);
1192         return err;
1193 }
1194
1195 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1196
1197 void board_nand_init(void)
1198 {
1199         struct nand_chip *nand = &nand_chip[0];
1200
1201         if (zynq_nand_init(nand, 0))
1202                 puts("ZYNQ NAND init failed\n");
1203 }