2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP22_DESC_ADDR_OFFS 8
147 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
152 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156 #define MVPP2_RXQ_THRESH_REG 0x204c
157 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
158 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159 #define MVPP2_RXQ_INDEX_REG 0x2050
160 #define MVPP2_TXQ_NUM_REG 0x2080
161 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165 #define MVPP2_TXQ_THRESH_REG 0x2094
166 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168 #define MVPP2_TXQ_INDEX_REG 0x2098
169 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
170 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175 #define MVPP2_TXQ_PENDING_REG 0x20a0
176 #define MVPP2_TXQ_PENDING_MASK 0x3fff
177 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
188 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
189 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
195 /* MBUS bridge registers */
196 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199 #define MVPP2_BASE_ADDR_ENABLE 0x4060
201 /* AXI Bridge Registers */
202 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
203 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
204 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
205 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
206 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
207 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
208 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
209 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
210 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
211 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
212 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
213 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
215 /* Values for AXI Bridge registers */
216 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
217 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
219 #define MVPP22_AXI_CODE_CACHE_OFFS 0
220 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
222 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
223 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
224 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
226 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
227 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
229 /* Interrupt Cause and Mask registers */
230 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
231 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
233 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
238 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
241 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
242 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
243 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
244 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
246 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
247 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
248 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
249 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
250 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
251 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
252 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
253 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
254 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
255 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
256 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
257 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
258 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
259 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
260 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
261 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
262 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
263 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
265 /* Buffer Manager registers */
266 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
267 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
268 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
269 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
270 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
271 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
272 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
273 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
274 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
275 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
276 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
277 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
278 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
279 #define MVPP2_BM_START_MASK BIT(0)
280 #define MVPP2_BM_STOP_MASK BIT(1)
281 #define MVPP2_BM_STATE_MASK BIT(4)
282 #define MVPP2_BM_LOW_THRESH_OFFS 8
283 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
284 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_LOW_THRESH_OFFS)
286 #define MVPP2_BM_HIGH_THRESH_OFFS 16
287 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
288 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
289 MVPP2_BM_HIGH_THRESH_OFFS)
290 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
291 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
292 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
293 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
294 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
295 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
296 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
297 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
298 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
299 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
300 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
301 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
302 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
303 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
304 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
305 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
306 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
307 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
308 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
309 #define MVPP21_BM_MC_RLS_REG 0x64c4
310 #define MVPP2_BM_MC_ID_MASK 0xfff
311 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
312 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
313 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
314 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
315 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
316 #define MVPP22_BM_MC_RLS_REG 0x64d4
318 /* TX Scheduler registers */
319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
326 #define MVPP2_TXP_MTU_MAX 0x7FFFF
327 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
342 /* TX general registers */
343 #define MVPP2_TX_SNOOP_REG 0x8800
344 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
345 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
348 #define MVPP2_SRC_ADDR_MIDDLE 0x24
349 #define MVPP2_SRC_ADDR_HIGH 0x28
350 #define MVPP2_PHY_AN_CFG0_REG 0x34
351 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
352 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
353 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
355 /* Per-port registers */
356 #define MVPP2_GMAC_CTRL_0_REG 0x0
357 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
358 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
359 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
360 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
361 #define MVPP2_GMAC_CTRL_1_REG 0x4
362 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
363 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
364 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
365 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
366 #define MVPP2_GMAC_SA_LOW_OFFS 7
367 #define MVPP2_GMAC_CTRL_2_REG 0x8
368 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
369 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
370 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
371 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
372 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
373 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
374 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
375 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
376 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
377 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
378 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
379 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
380 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
381 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
382 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
383 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
384 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
385 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
387 #define MVPP22_SMI_MISC_CFG_REG 0x1204
388 #define MVPP22_SMI_POLLING_EN BIT(10)
390 #define MVPP22_PORT_BASE 0x30e00
391 #define MVPP22_PORT_OFFSET 0x1000
393 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
395 /* Descriptor ring Macros */
396 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
397 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
399 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
400 #define MVPP21_SMI 0x0054
401 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
402 #define MVPP22_SMI 0x1200
403 #define MVPP2_PHY_REG_MASK 0x1f
404 /* SMI register fields */
405 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
406 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
407 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
408 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
409 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
410 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
411 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
412 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
414 #define MVPP2_PHY_ADDR_MASK 0x1f
415 #define MVPP2_PHY_REG_MASK 0x1f
417 /* Various constants */
420 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
421 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
422 #define MVPP2_RX_COAL_PKTS 32
423 #define MVPP2_RX_COAL_USEC 100
425 /* The two bytes Marvell header. Either contains a special value used
426 * by Marvell switches when a specific hardware mode is enabled (not
427 * supported by this driver) or is filled automatically by zeroes on
428 * the RX side. Those two bytes being at the front of the Ethernet
429 * header, they allow to have the IP header aligned on a 4 bytes
430 * boundary automatically: the hardware skips those two bytes on its
433 #define MVPP2_MH_SIZE 2
434 #define MVPP2_ETH_TYPE_LEN 2
435 #define MVPP2_PPPOE_HDR_SIZE 8
436 #define MVPP2_VLAN_TAG_LEN 4
438 /* Lbtd 802.3 type */
439 #define MVPP2_IP_LBDT_TYPE 0xfffa
441 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
442 #define MVPP2_TX_CSUM_MAX_SIZE 9800
444 /* Timeout constants */
445 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
446 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
448 #define MVPP2_TX_MTU_MAX 0x7ffff
450 /* Maximum number of T-CONTs of PON port */
451 #define MVPP2_MAX_TCONT 16
453 /* Maximum number of supported ports */
454 #define MVPP2_MAX_PORTS 4
456 /* Maximum number of TXQs used by single port */
457 #define MVPP2_MAX_TXQ 8
459 /* Default number of TXQs in use */
460 #define MVPP2_DEFAULT_TXQ 1
462 /* Dfault number of RXQs in use */
463 #define MVPP2_DEFAULT_RXQ 1
464 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
466 /* Max number of Rx descriptors */
467 #define MVPP2_MAX_RXD 16
469 /* Max number of Tx descriptors */
470 #define MVPP2_MAX_TXD 16
472 /* Amount of Tx descriptors that can be reserved at once by CPU */
473 #define MVPP2_CPU_DESC_CHUNK 64
475 /* Max number of Tx descriptors in each aggregated queue */
476 #define MVPP2_AGGR_TXQ_SIZE 256
478 /* Descriptor aligned size */
479 #define MVPP2_DESC_ALIGNED_SIZE 32
481 /* Descriptor alignment mask */
482 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
484 /* RX FIFO constants */
485 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
486 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
487 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
488 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
489 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
490 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
491 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
492 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
493 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
495 /* TX general registers */
496 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
497 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
499 /* TX FIFO constants */
500 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
501 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
503 /* RX buffer constants */
504 #define MVPP2_SKB_SHINFO_SIZE \
507 #define MVPP2_RX_PKT_SIZE(mtu) \
508 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
509 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
511 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
512 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
513 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
514 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
516 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
518 /* IPv6 max L3 address size */
519 #define MVPP2_MAX_L3_ADDR_SIZE 16
522 #define MVPP2_F_LOOPBACK BIT(0)
524 /* Marvell tag types */
525 enum mvpp2_tag_type {
526 MVPP2_TAG_TYPE_NONE = 0,
527 MVPP2_TAG_TYPE_MH = 1,
528 MVPP2_TAG_TYPE_DSA = 2,
529 MVPP2_TAG_TYPE_EDSA = 3,
530 MVPP2_TAG_TYPE_VLAN = 4,
531 MVPP2_TAG_TYPE_LAST = 5
534 /* Parser constants */
535 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
536 #define MVPP2_PRS_TCAM_WORDS 6
537 #define MVPP2_PRS_SRAM_WORDS 4
538 #define MVPP2_PRS_FLOW_ID_SIZE 64
539 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
540 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
541 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
542 #define MVPP2_PRS_IPV4_HEAD 0x40
543 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
544 #define MVPP2_PRS_IPV4_MC 0xe0
545 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
546 #define MVPP2_PRS_IPV4_BC_MASK 0xff
547 #define MVPP2_PRS_IPV4_IHL 0x5
548 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
549 #define MVPP2_PRS_IPV6_MC 0xff
550 #define MVPP2_PRS_IPV6_MC_MASK 0xff
551 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
552 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
553 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
554 #define MVPP2_PRS_DBL_VLANS_MAX 100
557 * - lookup ID - 4 bits
559 * - additional information - 1 byte
560 * - header data - 8 bytes
561 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
563 #define MVPP2_PRS_AI_BITS 8
564 #define MVPP2_PRS_PORT_MASK 0xff
565 #define MVPP2_PRS_LU_MASK 0xf
566 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
567 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
568 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
569 (((offs) * 2) - ((offs) % 2) + 2)
570 #define MVPP2_PRS_TCAM_AI_BYTE 16
571 #define MVPP2_PRS_TCAM_PORT_BYTE 17
572 #define MVPP2_PRS_TCAM_LU_BYTE 20
573 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
574 #define MVPP2_PRS_TCAM_INV_WORD 5
575 /* Tcam entries ID */
576 #define MVPP2_PE_DROP_ALL 0
577 #define MVPP2_PE_FIRST_FREE_TID 1
578 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
579 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
580 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
581 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
582 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
583 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
584 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
585 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
586 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
587 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
588 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
589 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
590 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
591 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
592 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
593 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
594 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
595 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
596 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
597 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
598 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
599 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
600 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
601 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
602 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
605 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
607 #define MVPP2_PRS_SRAM_RI_OFFS 0
608 #define MVPP2_PRS_SRAM_RI_WORD 0
609 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
610 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
611 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
612 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
613 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
614 #define MVPP2_PRS_SRAM_UDF_OFFS 73
615 #define MVPP2_PRS_SRAM_UDF_BITS 8
616 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
617 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
618 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
619 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
620 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
621 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
622 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
623 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
624 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
625 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
626 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
627 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
628 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
629 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
630 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
631 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
632 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
633 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
634 #define MVPP2_PRS_SRAM_AI_OFFS 90
635 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
636 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
637 #define MVPP2_PRS_SRAM_AI_MASK 0xff
638 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
639 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
640 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
641 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
643 /* Sram result info bits assignment */
644 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
645 #define MVPP2_PRS_RI_DSA_MASK 0x2
646 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
647 #define MVPP2_PRS_RI_VLAN_NONE 0x0
648 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
649 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
650 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
651 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
652 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
653 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
654 #define MVPP2_PRS_RI_L2_UCAST 0x0
655 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
656 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
657 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
658 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
659 #define MVPP2_PRS_RI_L3_UN 0x0
660 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
661 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
662 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
663 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
664 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
665 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
666 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
667 #define MVPP2_PRS_RI_L3_UCAST 0x0
668 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
669 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
670 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
671 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
672 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
673 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
674 #define MVPP2_PRS_RI_L4_TCP BIT(22)
675 #define MVPP2_PRS_RI_L4_UDP BIT(23)
676 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
677 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
678 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
679 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
681 /* Sram additional info bits assignment */
682 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
683 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
684 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
685 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
686 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
687 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
688 #define MVPP2_PRS_SINGLE_VLAN_AI 0
689 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
692 #define MVPP2_PRS_TAGGED true
693 #define MVPP2_PRS_UNTAGGED false
694 #define MVPP2_PRS_EDSA true
695 #define MVPP2_PRS_DSA false
697 /* MAC entries, shadow udf */
699 MVPP2_PRS_UDF_MAC_DEF,
700 MVPP2_PRS_UDF_MAC_RANGE,
701 MVPP2_PRS_UDF_L2_DEF,
702 MVPP2_PRS_UDF_L2_DEF_COPY,
703 MVPP2_PRS_UDF_L2_USER,
707 enum mvpp2_prs_lookup {
721 enum mvpp2_prs_l3_cast {
722 MVPP2_PRS_L3_UNI_CAST,
723 MVPP2_PRS_L3_MULTI_CAST,
724 MVPP2_PRS_L3_BROAD_CAST
727 /* Classifier constants */
728 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
729 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
730 #define MVPP2_CLS_LKP_TBL_SIZE 64
733 #define MVPP2_BM_POOLS_NUM 1
734 #define MVPP2_BM_LONG_BUF_NUM 16
735 #define MVPP2_BM_SHORT_BUF_NUM 16
736 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
737 #define MVPP2_BM_POOL_PTR_ALIGN 128
738 #define MVPP2_BM_SWF_LONG_POOL(port) 0
740 /* BM cookie (32 bits) definition */
741 #define MVPP2_BM_COOKIE_POOL_OFFS 8
742 #define MVPP2_BM_COOKIE_CPU_OFFS 24
744 /* BM short pool packet size
745 * These value assure that for SWF the total number
746 * of bytes allocated for each buffer will be 512
748 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
758 /* Shared Packet Processor resources */
760 /* Shared registers' base addresses */
762 void __iomem *lms_base;
763 void __iomem *iface_base;
764 void __iomem *mdio_base;
766 /* List of pointers to port structures */
767 struct mvpp2_port **port_list;
769 /* Aggregated TXQs */
770 struct mvpp2_tx_queue *aggr_txqs;
773 struct mvpp2_bm_pool *bm_pools;
775 /* PRS shadow table */
776 struct mvpp2_prs_shadow *prs_shadow;
777 /* PRS auxiliary table for double vlan entries control */
778 bool *prs_double_vlans;
784 enum { MVPP21, MVPP22 } hw_version;
786 /* Maximum number of RXQs per port */
787 unsigned int max_port_rxqs;
794 struct mvpp2_pcpu_stats {
804 /* Index of the port from the "group of ports" complex point
813 /* Per-port registers' base address */
816 struct mvpp2_rx_queue **rxqs;
817 struct mvpp2_tx_queue **txqs;
821 u32 pending_cause_rx;
823 /* Per-CPU port control */
824 struct mvpp2_port_pcpu __percpu *pcpu;
831 struct mvpp2_pcpu_stats __percpu *stats;
833 struct phy_device *phy_dev;
834 phy_interface_t phy_interface;
842 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
844 struct mvpp2_bm_pool *pool_long;
845 struct mvpp2_bm_pool *pool_short;
847 /* Index of first port's physical RXQ */
850 u8 dev_addr[ETH_ALEN];
853 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
854 * layout of the transmit and reception DMA descriptors, and their
855 * layout is therefore defined by the hardware design
858 #define MVPP2_TXD_L3_OFF_SHIFT 0
859 #define MVPP2_TXD_IP_HLEN_SHIFT 8
860 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
861 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
862 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
863 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
864 #define MVPP2_TXD_L4_UDP BIT(24)
865 #define MVPP2_TXD_L3_IP6 BIT(26)
866 #define MVPP2_TXD_L_DESC BIT(28)
867 #define MVPP2_TXD_F_DESC BIT(29)
869 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
870 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
871 #define MVPP2_RXD_ERR_CRC 0x0
872 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
873 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
874 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
875 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
876 #define MVPP2_RXD_HWF_SYNC BIT(21)
877 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
878 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
879 #define MVPP2_RXD_L4_TCP BIT(25)
880 #define MVPP2_RXD_L4_UDP BIT(26)
881 #define MVPP2_RXD_L3_IP4 BIT(28)
882 #define MVPP2_RXD_L3_IP6 BIT(30)
883 #define MVPP2_RXD_BUF_HDR BIT(31)
885 /* HW TX descriptor for PPv2.1 */
886 struct mvpp21_tx_desc {
887 u32 command; /* Options used by HW for packet transmitting.*/
888 u8 packet_offset; /* the offset from the buffer beginning */
889 u8 phys_txq; /* destination queue ID */
890 u16 data_size; /* data size of transmitted packet in bytes */
891 u32 buf_dma_addr; /* physical addr of transmitted buffer */
892 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
893 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
894 u32 reserved2; /* reserved (for future use) */
897 /* HW RX descriptor for PPv2.1 */
898 struct mvpp21_rx_desc {
899 u32 status; /* info about received packet */
900 u16 reserved1; /* parser_info (for future use, PnC) */
901 u16 data_size; /* size of received packet in bytes */
902 u32 buf_dma_addr; /* physical address of the buffer */
903 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
904 u16 reserved2; /* gem_port_id (for future use, PON) */
905 u16 reserved3; /* csum_l4 (for future use, PnC) */
906 u8 reserved4; /* bm_qset (for future use, BM) */
908 u16 reserved6; /* classify_info (for future use, PnC) */
909 u32 reserved7; /* flow_id (for future use, PnC) */
913 /* HW TX descriptor for PPv2.2 */
914 struct mvpp22_tx_desc {
920 u64 buf_dma_addr_ptp;
924 /* HW RX descriptor for PPv2.2 */
925 struct mvpp22_rx_desc {
931 u64 buf_dma_addr_key_hash;
935 /* Opaque type used by the driver to manipulate the HW TX and RX
938 struct mvpp2_tx_desc {
940 struct mvpp21_tx_desc pp21;
941 struct mvpp22_tx_desc pp22;
945 struct mvpp2_rx_desc {
947 struct mvpp21_rx_desc pp21;
948 struct mvpp22_rx_desc pp22;
952 /* Per-CPU Tx queue control */
953 struct mvpp2_txq_pcpu {
956 /* Number of Tx DMA descriptors in the descriptor ring */
959 /* Number of currently used Tx DMA descriptor in the
964 /* Number of Tx DMA descriptors reserved for each CPU */
967 /* Index of last TX DMA descriptor that was inserted */
970 /* Index of the TX DMA descriptor to be cleaned up */
974 struct mvpp2_tx_queue {
975 /* Physical number of this Tx queue */
978 /* Logical number of this Tx queue */
981 /* Number of Tx DMA descriptors in the descriptor ring */
984 /* Number of currently used Tx DMA descriptor in the descriptor ring */
987 /* Per-CPU control of physical Tx queues */
988 struct mvpp2_txq_pcpu __percpu *pcpu;
992 /* Virtual address of thex Tx DMA descriptors array */
993 struct mvpp2_tx_desc *descs;
995 /* DMA address of the Tx DMA descriptors array */
996 dma_addr_t descs_dma;
998 /* Index of the last Tx DMA descriptor */
1001 /* Index of the next Tx DMA descriptor to process */
1002 int next_desc_to_proc;
1005 struct mvpp2_rx_queue {
1006 /* RX queue number, in the range 0-31 for physical RXQs */
1009 /* Num of rx descriptors in the rx descriptor ring */
1015 /* Virtual address of the RX DMA descriptors array */
1016 struct mvpp2_rx_desc *descs;
1018 /* DMA address of the RX DMA descriptors array */
1019 dma_addr_t descs_dma;
1021 /* Index of the last RX DMA descriptor */
1024 /* Index of the next RX DMA descriptor to process */
1025 int next_desc_to_proc;
1027 /* ID of port to which physical RXQ is mapped */
1030 /* Port's logic RXQ number to which physical RXQ is mapped */
1034 union mvpp2_prs_tcam_entry {
1035 u32 word[MVPP2_PRS_TCAM_WORDS];
1036 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1039 union mvpp2_prs_sram_entry {
1040 u32 word[MVPP2_PRS_SRAM_WORDS];
1041 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1044 struct mvpp2_prs_entry {
1046 union mvpp2_prs_tcam_entry tcam;
1047 union mvpp2_prs_sram_entry sram;
1050 struct mvpp2_prs_shadow {
1057 /* User defined offset */
1065 struct mvpp2_cls_flow_entry {
1067 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1070 struct mvpp2_cls_lookup_entry {
1076 struct mvpp2_bm_pool {
1077 /* Pool number in the range 0-7 */
1079 enum mvpp2_bm_type type;
1081 /* Buffer Pointers Pool External (BPPE) size */
1083 /* Number of buffers for this pool */
1085 /* Pool buffer size */
1090 /* BPPE virtual base address */
1091 unsigned long *virt_addr;
1092 /* BPPE DMA base address */
1093 dma_addr_t dma_addr;
1095 /* Ports using BM pool */
1098 /* Occupied buffers indicator */
1102 /* Static declaractions */
1104 /* Number of RXQs used by single port */
1105 static int rxq_number = MVPP2_DEFAULT_RXQ;
1106 /* Number of TXQs used by single port */
1107 static int txq_number = MVPP2_DEFAULT_TXQ;
1111 #define MVPP2_DRIVER_NAME "mvpp2"
1112 #define MVPP2_DRIVER_VERSION "1.0"
1115 * U-Boot internal data, mostly uncached buffers for descriptors and data
1117 struct buffer_location {
1118 struct mvpp2_tx_desc *aggr_tx_descs;
1119 struct mvpp2_tx_desc *tx_descs;
1120 struct mvpp2_rx_desc *rx_descs;
1121 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1122 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1127 * All 4 interfaces use the same global buffer, since only one interface
1128 * can be enabled at once
1130 static struct buffer_location buffer_loc;
1133 * Page table entries are set to 1MB, or multiples of 1MB
1134 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1136 #define BD_SPACE (1 << 20)
1138 /* Utility/helper methods */
1140 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1142 writel(data, priv->base + offset);
1145 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1147 return readl(priv->base + offset);
1150 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1151 struct mvpp2_tx_desc *tx_desc,
1152 dma_addr_t dma_addr)
1154 if (port->priv->hw_version == MVPP21) {
1155 tx_desc->pp21.buf_dma_addr = dma_addr;
1157 u64 val = (u64)dma_addr;
1159 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1160 tx_desc->pp22.buf_dma_addr_ptp |= val;
1164 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1165 struct mvpp2_tx_desc *tx_desc,
1168 if (port->priv->hw_version == MVPP21)
1169 tx_desc->pp21.data_size = size;
1171 tx_desc->pp22.data_size = size;
1174 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1175 struct mvpp2_tx_desc *tx_desc,
1178 if (port->priv->hw_version == MVPP21)
1179 tx_desc->pp21.phys_txq = txq;
1181 tx_desc->pp22.phys_txq = txq;
1184 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1185 struct mvpp2_tx_desc *tx_desc,
1186 unsigned int command)
1188 if (port->priv->hw_version == MVPP21)
1189 tx_desc->pp21.command = command;
1191 tx_desc->pp22.command = command;
1194 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1195 struct mvpp2_tx_desc *tx_desc,
1196 unsigned int offset)
1198 if (port->priv->hw_version == MVPP21)
1199 tx_desc->pp21.packet_offset = offset;
1201 tx_desc->pp22.packet_offset = offset;
1204 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1205 struct mvpp2_rx_desc *rx_desc)
1207 if (port->priv->hw_version == MVPP21)
1208 return rx_desc->pp21.buf_dma_addr;
1210 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1213 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1214 struct mvpp2_rx_desc *rx_desc)
1216 if (port->priv->hw_version == MVPP21)
1217 return rx_desc->pp21.buf_cookie;
1219 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1222 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1223 struct mvpp2_rx_desc *rx_desc)
1225 if (port->priv->hw_version == MVPP21)
1226 return rx_desc->pp21.data_size;
1228 return rx_desc->pp22.data_size;
1231 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1232 struct mvpp2_rx_desc *rx_desc)
1234 if (port->priv->hw_version == MVPP21)
1235 return rx_desc->pp21.status;
1237 return rx_desc->pp22.status;
1240 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1242 txq_pcpu->txq_get_index++;
1243 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1244 txq_pcpu->txq_get_index = 0;
1247 /* Get number of physical egress port */
1248 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1250 return MVPP2_MAX_TCONT + port->id;
1253 /* Get number of physical TXQ */
1254 static inline int mvpp2_txq_phys(int port, int txq)
1256 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1259 /* Parser configuration routines */
1261 /* Update parser tcam and sram hw entries */
1262 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1266 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1269 /* Clear entry invalidation bit */
1270 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1272 /* Write tcam index - indirect access */
1273 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1274 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1275 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1277 /* Write sram index - indirect access */
1278 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1279 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1280 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1285 /* Read tcam entry from hw */
1286 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1290 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1293 /* Write tcam index - indirect access */
1294 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1296 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1297 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1298 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1299 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1301 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1302 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1304 /* Write sram index - indirect access */
1305 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1306 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1307 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1312 /* Invalidate tcam hw entry */
1313 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1315 /* Write index - indirect access */
1316 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1317 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1318 MVPP2_PRS_TCAM_INV_MASK);
1321 /* Enable shadow table entry and set its lookup ID */
1322 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1324 priv->prs_shadow[index].valid = true;
1325 priv->prs_shadow[index].lu = lu;
1328 /* Update ri fields in shadow table entry */
1329 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1330 unsigned int ri, unsigned int ri_mask)
1332 priv->prs_shadow[index].ri_mask = ri_mask;
1333 priv->prs_shadow[index].ri = ri;
1336 /* Update lookup field in tcam sw entry */
1337 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1339 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1341 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1342 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1345 /* Update mask for single port in tcam sw entry */
1346 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1347 unsigned int port, bool add)
1349 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1352 pe->tcam.byte[enable_off] &= ~(1 << port);
1354 pe->tcam.byte[enable_off] |= 1 << port;
1357 /* Update port map in tcam sw entry */
1358 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1361 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1362 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1364 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1365 pe->tcam.byte[enable_off] &= ~port_mask;
1366 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1369 /* Obtain port map from tcam sw entry */
1370 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1372 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1374 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1377 /* Set byte of data and its enable bits in tcam sw entry */
1378 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1379 unsigned int offs, unsigned char byte,
1380 unsigned char enable)
1382 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1383 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1386 /* Get byte of data and its enable bits from tcam sw entry */
1387 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1388 unsigned int offs, unsigned char *byte,
1389 unsigned char *enable)
1391 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1392 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1395 /* Set ethertype in tcam sw entry */
1396 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1397 unsigned short ethertype)
1399 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1400 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1403 /* Set bits in sram sw entry */
1404 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1407 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1410 /* Clear bits in sram sw entry */
1411 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1414 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1417 /* Update ri bits in sram sw entry */
1418 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1419 unsigned int bits, unsigned int mask)
1423 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1424 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1426 if (!(mask & BIT(i)))
1430 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1432 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1434 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1438 /* Update ai bits in sram sw entry */
1439 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1440 unsigned int bits, unsigned int mask)
1443 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1445 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1447 if (!(mask & BIT(i)))
1451 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1453 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1455 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1459 /* Read ai bits from sram sw entry */
1460 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1463 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1464 int ai_en_off = ai_off + 1;
1465 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1467 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1468 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1473 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1476 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1479 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1481 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1482 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1483 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1486 /* In the sram sw entry set sign and value of the next lookup offset
1487 * and the offset value generated to the classifier
1489 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1494 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1497 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1501 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1502 (unsigned char)shift;
1504 /* Reset and set operation */
1505 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1506 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1507 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1509 /* Set base offset as current */
1510 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1513 /* In the sram sw entry set sign and value of the user defined offset
1514 * generated to the classifier
1516 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1517 unsigned int type, int offset,
1522 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1523 offset = 0 - offset;
1525 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1529 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1530 MVPP2_PRS_SRAM_UDF_MASK);
1531 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1532 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1533 MVPP2_PRS_SRAM_UDF_BITS)] &=
1534 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1535 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1536 MVPP2_PRS_SRAM_UDF_BITS)] |=
1537 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1539 /* Set offset type */
1540 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1541 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1542 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1544 /* Set offset operation */
1545 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1546 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1547 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1549 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1550 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1551 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1552 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1554 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1555 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1556 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1558 /* Set base offset as current */
1559 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1562 /* Find parser flow entry */
1563 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1565 struct mvpp2_prs_entry *pe;
1568 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1571 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1573 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1574 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1577 if (!priv->prs_shadow[tid].valid ||
1578 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1582 mvpp2_prs_hw_read(priv, pe);
1583 bits = mvpp2_prs_sram_ai_get(pe);
1585 /* Sram store classification lookup ID in AI bits [5:0] */
1586 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1594 /* Return first free tcam index, seeking from start to end */
1595 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1603 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1604 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1606 for (tid = start; tid <= end; tid++) {
1607 if (!priv->prs_shadow[tid].valid)
1614 /* Enable/disable dropping all mac da's */
1615 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1617 struct mvpp2_prs_entry pe;
1619 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1620 /* Entry exist - update port only */
1621 pe.index = MVPP2_PE_DROP_ALL;
1622 mvpp2_prs_hw_read(priv, &pe);
1624 /* Entry doesn't exist - create new */
1625 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1626 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1627 pe.index = MVPP2_PE_DROP_ALL;
1629 /* Non-promiscuous mode for all ports - DROP unknown packets */
1630 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1631 MVPP2_PRS_RI_DROP_MASK);
1633 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1634 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1636 /* Update shadow table */
1637 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1639 /* Mask all ports */
1640 mvpp2_prs_tcam_port_map_set(&pe, 0);
1643 /* Update port mask */
1644 mvpp2_prs_tcam_port_set(&pe, port, add);
1646 mvpp2_prs_hw_write(priv, &pe);
1649 /* Set port to promiscuous mode */
1650 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1652 struct mvpp2_prs_entry pe;
1654 /* Promiscuous mode - Accept unknown packets */
1656 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1657 /* Entry exist - update port only */
1658 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1659 mvpp2_prs_hw_read(priv, &pe);
1661 /* Entry doesn't exist - create new */
1662 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1663 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1664 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1666 /* Continue - set next lookup */
1667 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1669 /* Set result info bits */
1670 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1671 MVPP2_PRS_RI_L2_CAST_MASK);
1673 /* Shift to ethertype */
1674 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1675 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1677 /* Mask all ports */
1678 mvpp2_prs_tcam_port_map_set(&pe, 0);
1680 /* Update shadow table */
1681 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1684 /* Update port mask */
1685 mvpp2_prs_tcam_port_set(&pe, port, add);
1687 mvpp2_prs_hw_write(priv, &pe);
1690 /* Accept multicast */
1691 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1694 struct mvpp2_prs_entry pe;
1695 unsigned char da_mc;
1697 /* Ethernet multicast address first byte is
1698 * 0x01 for IPv4 and 0x33 for IPv6
1700 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1702 if (priv->prs_shadow[index].valid) {
1703 /* Entry exist - update port only */
1705 mvpp2_prs_hw_read(priv, &pe);
1707 /* Entry doesn't exist - create new */
1708 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1709 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1712 /* Continue - set next lookup */
1713 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1715 /* Set result info bits */
1716 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1717 MVPP2_PRS_RI_L2_CAST_MASK);
1719 /* Update tcam entry data first byte */
1720 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1722 /* Shift to ethertype */
1723 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1724 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1726 /* Mask all ports */
1727 mvpp2_prs_tcam_port_map_set(&pe, 0);
1729 /* Update shadow table */
1730 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1733 /* Update port mask */
1734 mvpp2_prs_tcam_port_set(&pe, port, add);
1736 mvpp2_prs_hw_write(priv, &pe);
1739 /* Parser per-port initialization */
1740 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1741 int lu_max, int offset)
1746 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1747 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1748 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1749 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1751 /* Set maximum number of loops for packet received from port */
1752 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1753 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1754 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1755 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1757 /* Set initial offset for packet header extraction for the first
1760 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1761 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1762 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1763 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1766 /* Default flow entries initialization for all ports */
1767 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1769 struct mvpp2_prs_entry pe;
1772 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1773 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1774 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1775 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1777 /* Mask all ports */
1778 mvpp2_prs_tcam_port_map_set(&pe, 0);
1781 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1782 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1784 /* Update shadow table and hw entry */
1785 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1786 mvpp2_prs_hw_write(priv, &pe);
1790 /* Set default entry for Marvell Header field */
1791 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1793 struct mvpp2_prs_entry pe;
1795 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1797 pe.index = MVPP2_PE_MH_DEFAULT;
1798 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1799 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1800 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1801 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1803 /* Unmask all ports */
1804 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1806 /* Update shadow table and hw entry */
1807 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1808 mvpp2_prs_hw_write(priv, &pe);
1811 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1812 * multicast MAC addresses
1814 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1816 struct mvpp2_prs_entry pe;
1818 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1820 /* Non-promiscuous mode for all ports - DROP unknown packets */
1821 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1822 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1824 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1825 MVPP2_PRS_RI_DROP_MASK);
1826 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1827 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1829 /* Unmask all ports */
1830 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1832 /* Update shadow table and hw entry */
1833 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1834 mvpp2_prs_hw_write(priv, &pe);
1836 /* place holders only - no ports */
1837 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1838 mvpp2_prs_mac_promisc_set(priv, 0, false);
1839 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1840 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1843 /* Match basic ethertypes */
1844 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1846 struct mvpp2_prs_entry pe;
1849 /* Ethertype: PPPoE */
1850 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1851 MVPP2_PE_LAST_FREE_TID);
1855 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1856 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1859 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1861 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1862 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1863 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1864 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1865 MVPP2_PRS_RI_PPPOE_MASK);
1867 /* Update shadow table and hw entry */
1868 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1869 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1870 priv->prs_shadow[pe.index].finish = false;
1871 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1872 MVPP2_PRS_RI_PPPOE_MASK);
1873 mvpp2_prs_hw_write(priv, &pe);
1875 /* Ethertype: ARP */
1876 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1877 MVPP2_PE_LAST_FREE_TID);
1881 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1882 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1885 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1887 /* Generate flow in the next iteration*/
1888 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1889 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1890 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1891 MVPP2_PRS_RI_L3_PROTO_MASK);
1893 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1895 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1897 /* Update shadow table and hw entry */
1898 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1899 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1900 priv->prs_shadow[pe.index].finish = true;
1901 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1902 MVPP2_PRS_RI_L3_PROTO_MASK);
1903 mvpp2_prs_hw_write(priv, &pe);
1905 /* Ethertype: LBTD */
1906 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1907 MVPP2_PE_LAST_FREE_TID);
1911 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1912 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1915 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1917 /* Generate flow in the next iteration*/
1918 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1919 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1920 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1921 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1922 MVPP2_PRS_RI_CPU_CODE_MASK |
1923 MVPP2_PRS_RI_UDF3_MASK);
1925 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1927 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1929 /* Update shadow table and hw entry */
1930 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1931 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1932 priv->prs_shadow[pe.index].finish = true;
1933 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1934 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1935 MVPP2_PRS_RI_CPU_CODE_MASK |
1936 MVPP2_PRS_RI_UDF3_MASK);
1937 mvpp2_prs_hw_write(priv, &pe);
1939 /* Ethertype: IPv4 without options */
1940 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1941 MVPP2_PE_LAST_FREE_TID);
1945 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1946 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1949 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1950 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1951 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1952 MVPP2_PRS_IPV4_HEAD_MASK |
1953 MVPP2_PRS_IPV4_IHL_MASK);
1955 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1956 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1957 MVPP2_PRS_RI_L3_PROTO_MASK);
1958 /* Skip eth_type + 4 bytes of IP header */
1959 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1960 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1962 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1964 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1966 /* Update shadow table and hw entry */
1967 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1968 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1969 priv->prs_shadow[pe.index].finish = false;
1970 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1971 MVPP2_PRS_RI_L3_PROTO_MASK);
1972 mvpp2_prs_hw_write(priv, &pe);
1974 /* Ethertype: IPv4 with options */
1975 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1976 MVPP2_PE_LAST_FREE_TID);
1982 /* Clear tcam data before updating */
1983 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1984 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1986 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1987 MVPP2_PRS_IPV4_HEAD,
1988 MVPP2_PRS_IPV4_HEAD_MASK);
1990 /* Clear ri before updating */
1991 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1992 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1993 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1994 MVPP2_PRS_RI_L3_PROTO_MASK);
1996 /* Update shadow table and hw entry */
1997 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1998 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1999 priv->prs_shadow[pe.index].finish = false;
2000 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2001 MVPP2_PRS_RI_L3_PROTO_MASK);
2002 mvpp2_prs_hw_write(priv, &pe);
2004 /* Ethertype: IPv6 without options */
2005 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2006 MVPP2_PE_LAST_FREE_TID);
2010 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2011 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2014 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2016 /* Skip DIP of IPV6 header */
2017 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2018 MVPP2_MAX_L3_ADDR_SIZE,
2019 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2020 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2021 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2022 MVPP2_PRS_RI_L3_PROTO_MASK);
2024 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2026 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2028 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2029 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2030 priv->prs_shadow[pe.index].finish = false;
2031 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2032 MVPP2_PRS_RI_L3_PROTO_MASK);
2033 mvpp2_prs_hw_write(priv, &pe);
2035 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2036 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2037 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2038 pe.index = MVPP2_PE_ETH_TYPE_UN;
2040 /* Unmask all ports */
2041 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2043 /* Generate flow in the next iteration*/
2044 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2045 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2046 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2047 MVPP2_PRS_RI_L3_PROTO_MASK);
2048 /* Set L3 offset even it's unknown L3 */
2049 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2051 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2053 /* Update shadow table and hw entry */
2054 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2055 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2056 priv->prs_shadow[pe.index].finish = true;
2057 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2058 MVPP2_PRS_RI_L3_PROTO_MASK);
2059 mvpp2_prs_hw_write(priv, &pe);
2064 /* Parser default initialization */
2065 static int mvpp2_prs_default_init(struct udevice *dev,
2070 /* Enable tcam table */
2071 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2073 /* Clear all tcam and sram entries */
2074 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2075 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2076 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2077 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2079 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2080 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2081 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2084 /* Invalidate all tcam entries */
2085 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2086 mvpp2_prs_hw_inv(priv, index);
2088 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2089 sizeof(struct mvpp2_prs_shadow),
2091 if (!priv->prs_shadow)
2094 /* Always start from lookup = 0 */
2095 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2096 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2097 MVPP2_PRS_PORT_LU_MAX, 0);
2099 mvpp2_prs_def_flow_init(priv);
2101 mvpp2_prs_mh_init(priv);
2103 mvpp2_prs_mac_init(priv);
2105 err = mvpp2_prs_etype_init(priv);
2112 /* Compare MAC DA with tcam entry data */
2113 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2114 const u8 *da, unsigned char *mask)
2116 unsigned char tcam_byte, tcam_mask;
2119 for (index = 0; index < ETH_ALEN; index++) {
2120 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2121 if (tcam_mask != mask[index])
2124 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2131 /* Find tcam entry with matched pair <MAC DA, port> */
2132 static struct mvpp2_prs_entry *
2133 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2134 unsigned char *mask, int udf_type)
2136 struct mvpp2_prs_entry *pe;
2139 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2142 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2144 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2145 for (tid = MVPP2_PE_FIRST_FREE_TID;
2146 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2147 unsigned int entry_pmap;
2149 if (!priv->prs_shadow[tid].valid ||
2150 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2151 (priv->prs_shadow[tid].udf != udf_type))
2155 mvpp2_prs_hw_read(priv, pe);
2156 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2158 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2167 /* Update parser's mac da entry */
2168 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2169 const u8 *da, bool add)
2171 struct mvpp2_prs_entry *pe;
2172 unsigned int pmap, len, ri;
2173 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2176 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2177 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2178 MVPP2_PRS_UDF_MAC_DEF);
2185 /* Create new TCAM entry */
2186 /* Find first range mac entry*/
2187 for (tid = MVPP2_PE_FIRST_FREE_TID;
2188 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2189 if (priv->prs_shadow[tid].valid &&
2190 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2191 (priv->prs_shadow[tid].udf ==
2192 MVPP2_PRS_UDF_MAC_RANGE))
2195 /* Go through the all entries from first to last */
2196 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2201 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2204 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2207 /* Mask all ports */
2208 mvpp2_prs_tcam_port_map_set(pe, 0);
2211 /* Update port mask */
2212 mvpp2_prs_tcam_port_set(pe, port, add);
2214 /* Invalidate the entry if no ports are left enabled */
2215 pmap = mvpp2_prs_tcam_port_map_get(pe);
2221 mvpp2_prs_hw_inv(priv, pe->index);
2222 priv->prs_shadow[pe->index].valid = false;
2227 /* Continue - set next lookup */
2228 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2230 /* Set match on DA */
2233 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2235 /* Set result info bits */
2236 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2238 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2239 MVPP2_PRS_RI_MAC_ME_MASK);
2240 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2241 MVPP2_PRS_RI_MAC_ME_MASK);
2243 /* Shift to ethertype */
2244 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2245 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2247 /* Update shadow table and hw entry */
2248 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2249 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2250 mvpp2_prs_hw_write(priv, pe);
2257 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2261 /* Remove old parser entry */
2262 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2267 /* Add new parser entry */
2268 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2272 /* Set addr in the device */
2273 memcpy(port->dev_addr, da, ETH_ALEN);
2278 /* Set prs flow for the port */
2279 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2281 struct mvpp2_prs_entry *pe;
2284 pe = mvpp2_prs_flow_find(port->priv, port->id);
2286 /* Such entry not exist */
2288 /* Go through the all entires from last to first */
2289 tid = mvpp2_prs_tcam_first_free(port->priv,
2290 MVPP2_PE_LAST_FREE_TID,
2291 MVPP2_PE_FIRST_FREE_TID);
2295 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2299 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2303 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2304 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2306 /* Update shadow table */
2307 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2310 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2311 mvpp2_prs_hw_write(port->priv, pe);
2317 /* Classifier configuration routines */
2319 /* Update classification flow table registers */
2320 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2321 struct mvpp2_cls_flow_entry *fe)
2323 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2324 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2325 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2326 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2329 /* Update classification lookup table register */
2330 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2331 struct mvpp2_cls_lookup_entry *le)
2335 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2336 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2337 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2340 /* Classifier default initialization */
2341 static void mvpp2_cls_init(struct mvpp2 *priv)
2343 struct mvpp2_cls_lookup_entry le;
2344 struct mvpp2_cls_flow_entry fe;
2347 /* Enable classifier */
2348 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2350 /* Clear classifier flow table */
2351 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2352 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2354 mvpp2_cls_flow_write(priv, &fe);
2357 /* Clear classifier lookup table */
2359 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2362 mvpp2_cls_lookup_write(priv, &le);
2365 mvpp2_cls_lookup_write(priv, &le);
2369 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2371 struct mvpp2_cls_lookup_entry le;
2374 /* Set way for the port */
2375 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2376 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2377 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2379 /* Pick the entry to be accessed in lookup ID decoding table
2380 * according to the way and lkpid.
2382 le.lkpid = port->id;
2386 /* Set initial CPU queue for receiving packets */
2387 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2388 le.data |= port->first_rxq;
2390 /* Disable classification engines */
2391 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2393 /* Update lookup ID table entry */
2394 mvpp2_cls_lookup_write(port->priv, &le);
2397 /* Set CPU queue number for oversize packets */
2398 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2402 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2403 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2405 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2406 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2408 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2409 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2410 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2413 /* Buffer Manager configuration routines */
2416 static int mvpp2_bm_pool_create(struct udevice *dev,
2418 struct mvpp2_bm_pool *bm_pool, int size)
2422 /* Number of buffer pointers must be a multiple of 16, as per
2423 * hardware constraints
2425 if (!IS_ALIGNED(size, 16))
2428 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2429 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2430 if (!bm_pool->virt_addr)
2433 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2434 MVPP2_BM_POOL_PTR_ALIGN)) {
2435 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2436 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2440 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2441 lower_32_bits(bm_pool->dma_addr));
2442 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2444 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2445 val |= MVPP2_BM_START_MASK;
2446 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2448 bm_pool->type = MVPP2_BM_FREE;
2449 bm_pool->size = size;
2450 bm_pool->pkt_size = 0;
2451 bm_pool->buf_num = 0;
2456 /* Set pool buffer size */
2457 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2458 struct mvpp2_bm_pool *bm_pool,
2463 bm_pool->buf_size = buf_size;
2465 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2466 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2469 /* Free all buffers from the pool */
2470 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2471 struct mvpp2_bm_pool *bm_pool)
2473 bm_pool->buf_num = 0;
2477 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2479 struct mvpp2_bm_pool *bm_pool)
2483 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2484 if (bm_pool->buf_num) {
2485 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2490 val |= MVPP2_BM_STOP_MASK;
2491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2496 static int mvpp2_bm_pools_init(struct udevice *dev,
2500 struct mvpp2_bm_pool *bm_pool;
2502 /* Create all pools with maximum size */
2503 size = MVPP2_BM_POOL_SIZE_MAX;
2504 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2505 bm_pool = &priv->bm_pools[i];
2507 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2509 goto err_unroll_pools;
2510 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2515 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2516 for (i = i - 1; i >= 0; i--)
2517 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2521 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2525 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2526 /* Mask BM all interrupts */
2527 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2528 /* Clear BM cause register */
2529 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2532 /* Allocate and initialize BM pools */
2533 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2534 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2535 if (!priv->bm_pools)
2538 err = mvpp2_bm_pools_init(dev, priv);
2544 /* Attach long pool to rxq */
2545 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2546 int lrxq, int long_pool)
2551 /* Get queue physical ID */
2552 prxq = port->rxqs[lrxq]->id;
2554 if (port->priv->hw_version == MVPP21)
2555 mask = MVPP21_RXQ_POOL_LONG_MASK;
2557 mask = MVPP22_RXQ_POOL_LONG_MASK;
2559 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2561 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2562 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2565 /* Set pool number in a BM cookie */
2566 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2570 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2571 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2576 /* Get pool number from a BM cookie */
2577 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2579 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2582 /* Release buffer to BM */
2583 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2584 dma_addr_t buf_dma_addr,
2585 unsigned long buf_phys_addr)
2587 if (port->priv->hw_version == MVPP22) {
2590 if (sizeof(dma_addr_t) == 8)
2591 val |= upper_32_bits(buf_dma_addr) &
2592 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2594 if (sizeof(phys_addr_t) == 8)
2595 val |= (upper_32_bits(buf_phys_addr)
2596 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2597 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2599 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2602 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2603 * returned in the "cookie" field of the RX
2604 * descriptor. Instead of storing the virtual address, we
2605 * store the physical address
2607 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2608 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2611 /* Refill BM pool */
2612 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2613 dma_addr_t dma_addr,
2614 phys_addr_t phys_addr)
2616 int pool = mvpp2_bm_cookie_pool_get(bm);
2618 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2621 /* Allocate buffers for the pool */
2622 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2623 struct mvpp2_bm_pool *bm_pool, int buf_num)
2628 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2629 netdev_err(port->dev,
2630 "cannot allocate %d buffers for pool %d\n",
2631 buf_num, bm_pool->id);
2635 for (i = 0; i < buf_num; i++) {
2636 mvpp2_bm_pool_put(port, bm_pool->id,
2637 (dma_addr_t)buffer_loc.rx_buffer[i],
2638 (unsigned long)buffer_loc.rx_buffer[i]);
2642 /* Update BM driver with number of buffers added to pool */
2643 bm_pool->buf_num += i;
2644 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2649 /* Notify the driver that BM pool is being used as specific type and return the
2650 * pool pointer on success
2652 static struct mvpp2_bm_pool *
2653 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2656 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2659 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2660 netdev_err(port->dev, "mixing pool types is forbidden\n");
2664 if (new_pool->type == MVPP2_BM_FREE)
2665 new_pool->type = type;
2667 /* Allocate buffers in case BM pool is used as long pool, but packet
2668 * size doesn't match MTU or BM pool hasn't being used yet
2670 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2671 (new_pool->pkt_size == 0)) {
2674 /* Set default buffer number or free all the buffers in case
2675 * the pool is not empty
2677 pkts_num = new_pool->buf_num;
2679 pkts_num = type == MVPP2_BM_SWF_LONG ?
2680 MVPP2_BM_LONG_BUF_NUM :
2681 MVPP2_BM_SHORT_BUF_NUM;
2683 mvpp2_bm_bufs_free(NULL,
2684 port->priv, new_pool);
2686 new_pool->pkt_size = pkt_size;
2688 /* Allocate buffers for this pool */
2689 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2690 if (num != pkts_num) {
2691 dev_err(dev, "pool %d: %d of %d allocated\n",
2692 new_pool->id, num, pkts_num);
2697 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2698 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2703 /* Initialize pools for swf */
2704 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2708 if (!port->pool_long) {
2710 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2713 if (!port->pool_long)
2716 port->pool_long->port_map |= (1 << port->id);
2718 for (rxq = 0; rxq < rxq_number; rxq++)
2719 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2725 /* Port configuration routines */
2727 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2731 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2733 switch (port->phy_interface) {
2734 case PHY_INTERFACE_MODE_SGMII:
2735 val |= MVPP2_GMAC_INBAND_AN_MASK;
2737 case PHY_INTERFACE_MODE_RGMII:
2738 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2740 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2743 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2746 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2750 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2751 val |= MVPP2_GMAC_FC_ADV_EN;
2752 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2755 static void mvpp2_port_enable(struct mvpp2_port *port)
2759 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2760 val |= MVPP2_GMAC_PORT_EN_MASK;
2761 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2762 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2765 static void mvpp2_port_disable(struct mvpp2_port *port)
2769 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2770 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2771 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2774 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2775 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2779 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2780 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2781 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2784 /* Configure loopback port */
2785 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2789 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2791 if (port->speed == 1000)
2792 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2794 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2796 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2797 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2799 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2801 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2804 static void mvpp2_port_reset(struct mvpp2_port *port)
2808 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2809 ~MVPP2_GMAC_PORT_RESET_MASK;
2810 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2812 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2813 MVPP2_GMAC_PORT_RESET_MASK)
2817 /* Change maximum receive size of the port */
2818 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2822 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2823 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2824 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2825 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2826 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2829 /* Set defaults to the MVPP2 port */
2830 static void mvpp2_defaults_set(struct mvpp2_port *port)
2832 int tx_port_num, val, queue, ptxq, lrxq;
2834 if (port->priv->hw_version == MVPP21) {
2835 /* Configure port to loopback if needed */
2836 if (port->flags & MVPP2_F_LOOPBACK)
2837 mvpp2_port_loopback_set(port);
2839 /* Update TX FIFO MIN Threshold */
2840 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2841 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2842 /* Min. TX threshold must be less than minimal packet length */
2843 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2844 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2847 /* Disable Legacy WRR, Disable EJP, Release from reset */
2848 tx_port_num = mvpp2_egress_port(port);
2849 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2851 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2853 /* Close bandwidth for all queues */
2854 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2855 ptxq = mvpp2_txq_phys(port->id, queue);
2856 mvpp2_write(port->priv,
2857 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2860 /* Set refill period to 1 usec, refill tokens
2861 * and bucket size to maximum
2863 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2864 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2865 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2866 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2867 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2868 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2869 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2872 /* Set MaximumLowLatencyPacketSize value to 256 */
2873 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2874 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2875 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2877 /* Enable Rx cache snoop */
2878 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2879 queue = port->rxqs[lrxq]->id;
2880 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2881 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2882 MVPP2_SNOOP_BUF_HDR_MASK;
2883 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2887 /* Enable/disable receiving packets */
2888 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2893 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2894 queue = port->rxqs[lrxq]->id;
2895 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2896 val &= ~MVPP2_RXQ_DISABLE_MASK;
2897 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2901 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2906 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2907 queue = port->rxqs[lrxq]->id;
2908 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2909 val |= MVPP2_RXQ_DISABLE_MASK;
2910 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2914 /* Enable transmit via physical egress queue
2915 * - HW starts take descriptors from DRAM
2917 static void mvpp2_egress_enable(struct mvpp2_port *port)
2921 int tx_port_num = mvpp2_egress_port(port);
2923 /* Enable all initialized TXs. */
2925 for (queue = 0; queue < txq_number; queue++) {
2926 struct mvpp2_tx_queue *txq = port->txqs[queue];
2928 if (txq->descs != NULL)
2929 qmap |= (1 << queue);
2932 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2933 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2936 /* Disable transmit via physical egress queue
2937 * - HW doesn't take descriptors from DRAM
2939 static void mvpp2_egress_disable(struct mvpp2_port *port)
2943 int tx_port_num = mvpp2_egress_port(port);
2945 /* Issue stop command for active channels only */
2946 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2947 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2948 MVPP2_TXP_SCHED_ENQ_MASK;
2950 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2951 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2953 /* Wait for all Tx activity to terminate. */
2956 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2957 netdev_warn(port->dev,
2958 "Tx stop timed out, status=0x%08x\n",
2965 /* Check port TX Command register that all
2966 * Tx queues are stopped
2968 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2969 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2972 /* Rx descriptors helper methods */
2974 /* Get number of Rx descriptors occupied by received packets */
2976 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2978 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2980 return val & MVPP2_RXQ_OCCUPIED_MASK;
2983 /* Update Rx queue status with the number of occupied and available
2984 * Rx descriptor slots.
2987 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2988 int used_count, int free_count)
2990 /* Decrement the number of used descriptors and increment count
2991 * increment the number of free descriptors.
2993 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2995 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2998 /* Get pointer to next RX descriptor to be processed by SW */
2999 static inline struct mvpp2_rx_desc *
3000 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3002 int rx_desc = rxq->next_desc_to_proc;
3004 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3005 prefetch(rxq->descs + rxq->next_desc_to_proc);
3006 return rxq->descs + rx_desc;
3009 /* Set rx queue offset */
3010 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3011 int prxq, int offset)
3015 /* Convert offset from bytes to units of 32 bytes */
3016 offset = offset >> 5;
3018 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3019 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3022 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3023 MVPP2_RXQ_PACKET_OFFSET_MASK);
3025 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3028 /* Obtain BM cookie information from descriptor */
3029 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3030 struct mvpp2_rx_desc *rx_desc)
3032 int cpu = smp_processor_id();
3035 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3036 MVPP2_RXD_BM_POOL_ID_MASK) >>
3037 MVPP2_RXD_BM_POOL_ID_OFFS;
3039 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3040 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3043 /* Tx descriptors helper methods */
3045 /* Get number of Tx descriptors waiting to be transmitted by HW */
3046 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3047 struct mvpp2_tx_queue *txq)
3051 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3052 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3054 return val & MVPP2_TXQ_PENDING_MASK;
3057 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3058 static struct mvpp2_tx_desc *
3059 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3061 int tx_desc = txq->next_desc_to_proc;
3063 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3064 return txq->descs + tx_desc;
3067 /* Update HW with number of aggregated Tx descriptors to be sent */
3068 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3070 /* aggregated access - relevant TXQ number is written in TX desc */
3071 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3074 /* Get number of sent descriptors and decrement counter.
3075 * The number of sent descriptors is returned.
3078 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3079 struct mvpp2_tx_queue *txq)
3083 /* Reading status reg resets transmitted descriptor counter */
3084 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3086 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3087 MVPP2_TRANSMITTED_COUNT_OFFSET;
3090 static void mvpp2_txq_sent_counter_clear(void *arg)
3092 struct mvpp2_port *port = arg;
3095 for (queue = 0; queue < txq_number; queue++) {
3096 int id = port->txqs[queue]->id;
3098 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3102 /* Set max sizes for Tx queues */
3103 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3106 int txq, tx_port_num;
3108 mtu = port->pkt_size * 8;
3109 if (mtu > MVPP2_TXP_MTU_MAX)
3110 mtu = MVPP2_TXP_MTU_MAX;
3112 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3115 /* Indirect access to registers */
3116 tx_port_num = mvpp2_egress_port(port);
3117 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3120 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3121 val &= ~MVPP2_TXP_MTU_MAX;
3123 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3125 /* TXP token size and all TXQs token size must be larger that MTU */
3126 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3127 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3130 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3132 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3135 for (txq = 0; txq < txq_number; txq++) {
3136 val = mvpp2_read(port->priv,
3137 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3138 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3142 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3144 mvpp2_write(port->priv,
3145 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3151 /* Free Tx queue skbuffs */
3152 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
3153 struct mvpp2_tx_queue *txq,
3154 struct mvpp2_txq_pcpu *txq_pcpu, int num)
3158 for (i = 0; i < num; i++)
3159 mvpp2_txq_inc_get(txq_pcpu);
3162 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
3165 int queue = fls(cause) - 1;
3167 return port->rxqs[queue];
3170 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
3173 int queue = fls(cause) - 1;
3175 return port->txqs[queue];
3178 /* Rx/Tx queue initialization/cleanup methods */
3180 /* Allocate and initialize descriptors for aggr TXQ */
3181 static int mvpp2_aggr_txq_init(struct udevice *dev,
3182 struct mvpp2_tx_queue *aggr_txq,
3183 int desc_num, int cpu,
3188 /* Allocate memory for TX descriptors */
3189 aggr_txq->descs = buffer_loc.aggr_tx_descs;
3190 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
3191 if (!aggr_txq->descs)
3194 /* Make sure descriptor address is cache line size aligned */
3195 BUG_ON(aggr_txq->descs !=
3196 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3198 aggr_txq->last_desc = aggr_txq->size - 1;
3200 /* Aggr TXQ no reset WA */
3201 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
3202 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
3204 /* Set Tx descriptors queue starting address indirect
3207 if (priv->hw_version == MVPP21)
3208 txq_dma = aggr_txq->descs_dma;
3210 txq_dma = aggr_txq->descs_dma >>
3211 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
3213 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
3214 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
3219 /* Create a specified Rx queue */
3220 static int mvpp2_rxq_init(struct mvpp2_port *port,
3221 struct mvpp2_rx_queue *rxq)
3226 rxq->size = port->rx_ring_size;
3228 /* Allocate memory for RX descriptors */
3229 rxq->descs = buffer_loc.rx_descs;
3230 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
3234 BUG_ON(rxq->descs !=
3235 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3237 rxq->last_desc = rxq->size - 1;
3239 /* Zero occupied and non-occupied counters - direct access */
3240 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3242 /* Set Rx descriptors queue starting address - indirect access */
3243 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3244 if (port->priv->hw_version == MVPP21)
3245 rxq_dma = rxq->descs_dma;
3247 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
3248 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
3249 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
3250 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
3253 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
3255 /* Add number of descriptors ready for receiving packets */
3256 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3261 /* Push packets received by the RXQ to BM pool */
3262 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3263 struct mvpp2_rx_queue *rxq)
3267 rx_received = mvpp2_rxq_received(port, rxq->id);
3271 for (i = 0; i < rx_received; i++) {
3272 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3273 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
3275 mvpp2_pool_refill(port, bm,
3276 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3277 mvpp2_rxdesc_cookie_get(port, rx_desc));
3279 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3282 /* Cleanup Rx queue */
3283 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3284 struct mvpp2_rx_queue *rxq)
3286 mvpp2_rxq_drop_pkts(port, rxq);
3290 rxq->next_desc_to_proc = 0;
3293 /* Clear Rx descriptors queue starting address and size;
3294 * free descriptor number
3296 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3297 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3298 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3299 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3302 /* Create and initialize a Tx queue */
3303 static int mvpp2_txq_init(struct mvpp2_port *port,
3304 struct mvpp2_tx_queue *txq)
3307 int cpu, desc, desc_per_txq, tx_port_num;
3308 struct mvpp2_txq_pcpu *txq_pcpu;
3310 txq->size = port->tx_ring_size;
3312 /* Allocate memory for Tx descriptors */
3313 txq->descs = buffer_loc.tx_descs;
3314 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
3318 /* Make sure descriptor address is cache line size aligned */
3319 BUG_ON(txq->descs !=
3320 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3322 txq->last_desc = txq->size - 1;
3324 /* Set Tx descriptors queue starting address - indirect access */
3325 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3326 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
3327 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3328 MVPP2_TXQ_DESC_SIZE_MASK);
3329 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3330 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3331 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3332 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3333 val &= ~MVPP2_TXQ_PENDING_MASK;
3334 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3336 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3337 * for each existing TXQ.
3338 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3339 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3342 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3343 (txq->log_id * desc_per_txq);
3345 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3346 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3347 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3349 /* WRR / EJP configuration - indirect access */
3350 tx_port_num = mvpp2_egress_port(port);
3351 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3353 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3354 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3355 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3356 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3357 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3359 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3360 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3363 for_each_present_cpu(cpu) {
3364 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3365 txq_pcpu->size = txq->size;
3371 /* Free allocated TXQ resources */
3372 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3373 struct mvpp2_tx_queue *txq)
3377 txq->next_desc_to_proc = 0;
3380 /* Set minimum bandwidth for disabled TXQs */
3381 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3383 /* Set Tx descriptors queue starting address and size */
3384 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3385 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3386 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3389 /* Cleanup Tx ports */
3390 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3392 struct mvpp2_txq_pcpu *txq_pcpu;
3393 int delay, pending, cpu;
3396 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3397 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3398 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3399 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3401 /* The napi queue has been stopped so wait for all packets
3402 * to be transmitted.
3406 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3407 netdev_warn(port->dev,
3408 "port %d: cleaning queue %d timed out\n",
3409 port->id, txq->log_id);
3415 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3418 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3419 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3421 for_each_present_cpu(cpu) {
3422 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3424 /* Release all packets */
3425 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3428 txq_pcpu->count = 0;
3429 txq_pcpu->txq_put_index = 0;
3430 txq_pcpu->txq_get_index = 0;
3434 /* Cleanup all Tx queues */
3435 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3437 struct mvpp2_tx_queue *txq;
3441 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3443 /* Reset Tx ports and delete Tx queues */
3444 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3445 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3447 for (queue = 0; queue < txq_number; queue++) {
3448 txq = port->txqs[queue];
3449 mvpp2_txq_clean(port, txq);
3450 mvpp2_txq_deinit(port, txq);
3453 mvpp2_txq_sent_counter_clear(port);
3455 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3456 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3459 /* Cleanup all Rx queues */
3460 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3464 for (queue = 0; queue < rxq_number; queue++)
3465 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3468 /* Init all Rx queues for port */
3469 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3473 for (queue = 0; queue < rxq_number; queue++) {
3474 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3481 mvpp2_cleanup_rxqs(port);
3485 /* Init all tx queues for port */
3486 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3488 struct mvpp2_tx_queue *txq;
3491 for (queue = 0; queue < txq_number; queue++) {
3492 txq = port->txqs[queue];
3493 err = mvpp2_txq_init(port, txq);
3498 mvpp2_txq_sent_counter_clear(port);
3502 mvpp2_cleanup_txqs(port);
3507 static void mvpp2_link_event(struct mvpp2_port *port)
3509 struct phy_device *phydev = port->phy_dev;
3510 int status_change = 0;
3514 if ((port->speed != phydev->speed) ||
3515 (port->duplex != phydev->duplex)) {
3518 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3519 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3520 MVPP2_GMAC_CONFIG_GMII_SPEED |
3521 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3522 MVPP2_GMAC_AN_SPEED_EN |
3523 MVPP2_GMAC_AN_DUPLEX_EN);
3526 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3528 if (phydev->speed == SPEED_1000)
3529 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3530 else if (phydev->speed == SPEED_100)
3531 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3533 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3535 port->duplex = phydev->duplex;
3536 port->speed = phydev->speed;
3540 if (phydev->link != port->link) {
3541 if (!phydev->link) {
3546 port->link = phydev->link;
3550 if (status_change) {
3552 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3553 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3554 MVPP2_GMAC_FORCE_LINK_DOWN);
3555 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3556 mvpp2_egress_enable(port);
3557 mvpp2_ingress_enable(port);
3559 mvpp2_ingress_disable(port);
3560 mvpp2_egress_disable(port);
3565 /* Main RX/TX processing routines */
3567 /* Display more error info */
3568 static void mvpp2_rx_error(struct mvpp2_port *port,
3569 struct mvpp2_rx_desc *rx_desc)
3571 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3572 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3574 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3575 case MVPP2_RXD_ERR_CRC:
3576 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
3579 case MVPP2_RXD_ERR_OVERRUN:
3580 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
3583 case MVPP2_RXD_ERR_RESOURCE:
3584 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
3590 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3591 static int mvpp2_rx_refill(struct mvpp2_port *port,
3592 struct mvpp2_bm_pool *bm_pool,
3593 u32 bm, dma_addr_t dma_addr)
3595 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
3599 /* Set hw internals when starting port */
3600 static void mvpp2_start_dev(struct mvpp2_port *port)
3602 mvpp2_gmac_max_rx_size_set(port);
3603 mvpp2_txp_max_tx_size_set(port);
3605 mvpp2_port_enable(port);
3608 /* Set hw internals when stopping port */
3609 static void mvpp2_stop_dev(struct mvpp2_port *port)
3611 /* Stop new packets from arriving to RXQs */
3612 mvpp2_ingress_disable(port);
3614 mvpp2_egress_disable(port);
3615 mvpp2_port_disable(port);
3618 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3620 struct phy_device *phy_dev;
3622 if (!port->init || port->link == 0) {
3623 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3624 port->phy_interface);
3625 port->phy_dev = phy_dev;
3627 netdev_err(port->dev, "cannot connect to phy\n");
3630 phy_dev->supported &= PHY_GBIT_FEATURES;
3631 phy_dev->advertising = phy_dev->supported;
3633 port->phy_dev = phy_dev;
3638 phy_config(phy_dev);
3639 phy_startup(phy_dev);
3640 if (!phy_dev->link) {
3641 printf("%s: No link\n", phy_dev->dev->name);
3647 mvpp2_egress_enable(port);
3648 mvpp2_ingress_enable(port);
3654 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3656 unsigned char mac_bcast[ETH_ALEN] = {
3657 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3660 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3662 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3665 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3666 port->dev_addr, true);
3668 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3671 err = mvpp2_prs_def_flow(port);
3673 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3677 /* Allocate the Rx/Tx queues */
3678 err = mvpp2_setup_rxqs(port);
3680 netdev_err(port->dev, "cannot allocate Rx queues\n");
3684 err = mvpp2_setup_txqs(port);
3686 netdev_err(port->dev, "cannot allocate Tx queues\n");
3690 err = mvpp2_phy_connect(dev, port);
3694 mvpp2_link_event(port);
3696 mvpp2_start_dev(port);
3701 /* No Device ops here in U-Boot */
3703 /* Driver initialization */
3705 static void mvpp2_port_power_up(struct mvpp2_port *port)
3707 struct mvpp2 *priv = port->priv;
3709 mvpp2_port_mii_set(port);
3710 mvpp2_port_periodic_xon_disable(port);
3711 if (priv->hw_version == MVPP21)
3712 mvpp2_port_fc_adv_enable(port);
3713 mvpp2_port_reset(port);
3716 /* Initialize port HW */
3717 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3719 struct mvpp2 *priv = port->priv;
3720 struct mvpp2_txq_pcpu *txq_pcpu;
3721 int queue, cpu, err;
3723 if (port->first_rxq + rxq_number >
3724 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3728 mvpp2_egress_disable(port);
3729 mvpp2_port_disable(port);
3731 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3736 /* Associate physical Tx queues to this port and initialize.
3737 * The mapping is predefined.
3739 for (queue = 0; queue < txq_number; queue++) {
3740 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3741 struct mvpp2_tx_queue *txq;
3743 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3747 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3752 txq->id = queue_phy_id;
3753 txq->log_id = queue;
3754 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3755 for_each_present_cpu(cpu) {
3756 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3757 txq_pcpu->cpu = cpu;
3760 port->txqs[queue] = txq;
3763 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3768 /* Allocate and initialize Rx queue for this port */
3769 for (queue = 0; queue < rxq_number; queue++) {
3770 struct mvpp2_rx_queue *rxq;
3772 /* Map physical Rx queue to port's logical Rx queue */
3773 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3776 /* Map this Rx queue to a physical queue */
3777 rxq->id = port->first_rxq + queue;
3778 rxq->port = port->id;
3779 rxq->logic_rxq = queue;
3781 port->rxqs[queue] = rxq;
3784 /* Configure Rx queue group interrupt for this port */
3785 if (priv->hw_version == MVPP21) {
3786 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
3791 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
3792 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
3794 val = (CONFIG_MV_ETH_RXQ <<
3795 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
3796 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
3799 /* Create Rx descriptor rings */
3800 for (queue = 0; queue < rxq_number; queue++) {
3801 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3803 rxq->size = port->rx_ring_size;
3804 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3805 rxq->time_coal = MVPP2_RX_COAL_USEC;
3808 mvpp2_ingress_disable(port);
3810 /* Port default configuration */
3811 mvpp2_defaults_set(port);
3813 /* Port's classifier configuration */
3814 mvpp2_cls_oversize_rxq_set(port);
3815 mvpp2_cls_port_config(port);
3817 /* Provide an initial Rx packet size */
3818 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3820 /* Initialize pools for swf */
3821 err = mvpp2_swf_bm_pool_init(port);
3828 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
3830 int port_node = dev_of_offset(dev);
3831 const char *phy_mode_str;
3837 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3839 dev_err(&pdev->dev, "missing phy\n");
3843 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3845 phy_mode = phy_get_interface_by_name(phy_mode_str);
3846 if (phy_mode == -1) {
3847 dev_err(&pdev->dev, "incorrect phy mode\n");
3851 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3853 dev_err(&pdev->dev, "missing port-id value\n");
3859 * Not sure if this DT property "phy-speed" will get accepted, so
3860 * this might change later
3862 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
3863 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
3866 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3869 if (port->priv->hw_version == MVPP21)
3870 port->first_rxq = port->id * rxq_number;
3872 port->first_rxq = port->id * port->priv->max_port_rxqs;
3873 port->phy_node = phy_node;
3874 port->phy_interface = phy_mode;
3875 port->phyaddr = phyaddr;
3880 /* Ports initialization */
3881 static int mvpp2_port_probe(struct udevice *dev,
3882 struct mvpp2_port *port,
3888 port->tx_ring_size = MVPP2_MAX_TXD;
3889 port->rx_ring_size = MVPP2_MAX_RXD;
3891 err = mvpp2_port_init(dev, port);
3893 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
3896 mvpp2_port_power_up(port);
3898 priv->port_list[port->id] = port;
3902 /* Initialize decoding windows */
3903 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3909 for (i = 0; i < 6; i++) {
3910 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3911 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3914 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3919 for (i = 0; i < dram->num_cs; i++) {
3920 const struct mbus_dram_window *cs = dram->cs + i;
3922 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3923 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3924 dram->mbus_dram_target_id);
3926 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3927 (cs->size - 1) & 0xffff0000);
3929 win_enable |= (1 << i);
3932 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3935 /* Initialize Rx FIFO's */
3936 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3940 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3941 if (priv->hw_version == MVPP22) {
3944 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3945 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
3947 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3948 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
3949 } else if (port == 1) {
3951 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3952 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
3954 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3955 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
3958 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3959 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
3961 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3962 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
3965 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3966 MVPP21_RX_FIFO_PORT_DATA_SIZE);
3967 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3968 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
3972 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3973 MVPP2_RX_FIFO_PORT_MIN_PKT);
3974 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3977 /* Initialize Tx FIFO's */
3978 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
3982 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3983 /* Port 0 supports 10KB TX FIFO */
3985 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
3986 MVPP22_TX_FIFO_SIZE_MASK;
3988 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
3989 MVPP22_TX_FIFO_SIZE_MASK;
3991 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
3995 static void mvpp2_axi_init(struct mvpp2 *priv)
3997 u32 val, rdval, wrval;
3999 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4001 /* AXI Bridge Configuration */
4003 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4004 << MVPP22_AXI_ATTR_CACHE_OFFS;
4005 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4006 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4008 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4009 << MVPP22_AXI_ATTR_CACHE_OFFS;
4010 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4011 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4014 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4015 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4018 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4019 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4020 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4021 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4024 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4025 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4027 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4028 << MVPP22_AXI_CODE_CACHE_OFFS;
4029 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4030 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4031 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4032 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4034 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4035 << MVPP22_AXI_CODE_CACHE_OFFS;
4036 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4037 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4039 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4041 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4042 << MVPP22_AXI_CODE_CACHE_OFFS;
4043 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4044 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4046 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4049 /* Initialize network controller common part HW */
4050 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4052 const struct mbus_dram_target_info *dram_target_info;
4056 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4057 if ((rxq_number > priv->max_port_rxqs) ||
4058 (txq_number > MVPP2_MAX_TXQ)) {
4059 dev_err(&pdev->dev, "invalid queue size parameter\n");
4063 /* MBUS windows configuration */
4064 dram_target_info = mvebu_mbus_dram_info();
4065 if (dram_target_info)
4066 mvpp2_conf_mbus_windows(dram_target_info, priv);
4068 if (priv->hw_version == MVPP22)
4069 mvpp2_axi_init(priv);
4071 /* Disable HW PHY polling */
4072 if (priv->hw_version == MVPP21) {
4073 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4074 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4075 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4077 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4078 val &= ~MVPP22_SMI_POLLING_EN;
4079 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4082 /* Allocate and initialize aggregated TXQs */
4083 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
4084 sizeof(struct mvpp2_tx_queue),
4086 if (!priv->aggr_txqs)
4089 for_each_present_cpu(i) {
4090 priv->aggr_txqs[i].id = i;
4091 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
4092 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
4093 MVPP2_AGGR_TXQ_SIZE, i, priv);
4099 mvpp2_rx_fifo_init(priv);
4102 if (priv->hw_version == MVPP22)
4103 mvpp2_tx_fifo_init(priv);
4105 /* Reset Rx queue group interrupt configuration */
4106 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
4107 if (priv->hw_version == MVPP21) {
4108 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
4114 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4115 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4117 val = (CONFIG_MV_ETH_RXQ <<
4118 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4120 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4124 if (priv->hw_version == MVPP21)
4125 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
4126 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
4128 /* Allow cache snoop when transmiting packets */
4129 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
4131 /* Buffer Manager initialization */
4132 err = mvpp2_bm_init(dev, priv);
4136 /* Parser default initialization */
4137 err = mvpp2_prs_default_init(dev, priv);
4141 /* Classifier default initialization */
4142 mvpp2_cls_init(priv);
4147 /* SMI / MDIO functions */
4149 static int smi_wait_ready(struct mvpp2 *priv)
4151 u32 timeout = MVPP2_SMI_TIMEOUT;
4154 /* wait till the SMI is not busy */
4156 /* read smi register */
4157 smi_reg = readl(priv->mdio_base);
4158 if (timeout-- == 0) {
4159 printf("Error: SMI busy timeout\n");
4162 } while (smi_reg & MVPP2_SMI_BUSY);
4168 * mpp2_mdio_read - miiphy_read callback function.
4170 * Returns 16bit phy register value, or 0xffff on error
4172 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
4174 struct mvpp2 *priv = bus->priv;
4178 /* check parameters */
4179 if (addr > MVPP2_PHY_ADDR_MASK) {
4180 printf("Error: Invalid PHY address %d\n", addr);
4184 if (reg > MVPP2_PHY_REG_MASK) {
4185 printf("Err: Invalid register offset %d\n", reg);
4189 /* wait till the SMI is not busy */
4190 if (smi_wait_ready(priv) < 0)
4193 /* fill the phy address and regiser offset and read opcode */
4194 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4195 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
4196 | MVPP2_SMI_OPCODE_READ;
4198 /* write the smi register */
4199 writel(smi_reg, priv->mdio_base);
4201 /* wait till read value is ready */
4202 timeout = MVPP2_SMI_TIMEOUT;
4205 /* read smi register */
4206 smi_reg = readl(priv->mdio_base);
4207 if (timeout-- == 0) {
4208 printf("Err: SMI read ready timeout\n");
4211 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
4213 /* Wait for the data to update in the SMI register */
4214 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
4217 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
4221 * mpp2_mdio_write - miiphy_write callback function.
4223 * Returns 0 if write succeed, -EINVAL on bad parameters
4226 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
4229 struct mvpp2 *priv = bus->priv;
4232 /* check parameters */
4233 if (addr > MVPP2_PHY_ADDR_MASK) {
4234 printf("Error: Invalid PHY address %d\n", addr);
4238 if (reg > MVPP2_PHY_REG_MASK) {
4239 printf("Err: Invalid register offset %d\n", reg);
4243 /* wait till the SMI is not busy */
4244 if (smi_wait_ready(priv) < 0)
4247 /* fill the phy addr and reg offset and write opcode and data */
4248 smi_reg = value << MVPP2_SMI_DATA_OFFS;
4249 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4250 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
4251 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
4253 /* write the smi register */
4254 writel(smi_reg, priv->mdio_base);
4259 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
4261 struct mvpp2_port *port = dev_get_priv(dev);
4262 struct mvpp2_rx_desc *rx_desc;
4263 struct mvpp2_bm_pool *bm_pool;
4264 dma_addr_t dma_addr;
4266 int pool, rx_bytes, err;
4268 struct mvpp2_rx_queue *rxq;
4269 u32 cause_rx_tx, cause_rx, cause_misc;
4272 cause_rx_tx = mvpp2_read(port->priv,
4273 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4274 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4275 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4276 if (!cause_rx_tx && !cause_misc)
4279 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
4281 /* Process RX packets */
4282 cause_rx |= port->pending_cause_rx;
4283 rxq = mvpp2_get_rx_queue(port, cause_rx);
4285 /* Get number of received packets and clamp the to-do */
4286 rx_received = mvpp2_rxq_received(port, rxq->id);
4288 /* Return if no packets are received */
4292 rx_desc = mvpp2_rxq_next_desc_get(rxq);
4293 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
4294 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
4295 rx_bytes -= MVPP2_MH_SIZE;
4296 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
4298 bm = mvpp2_bm_cookie_build(port, rx_desc);
4299 pool = mvpp2_bm_cookie_pool_get(bm);
4300 bm_pool = &port->priv->bm_pools[pool];
4302 /* In case of an error, release the requested buffer pointer
4303 * to the Buffer Manager. This request process is controlled
4304 * by the hardware, and the information about the buffer is
4305 * comprised by the RX descriptor.
4307 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
4308 mvpp2_rx_error(port, rx_desc);
4309 /* Return the buffer to the pool */
4310 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
4314 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
4316 netdev_err(port->dev, "failed to refill BM pools\n");
4320 /* Update Rx queue management counters */
4322 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
4324 /* give packet to stack - skip on first n bytes */
4325 data = (u8 *)dma_addr + 2 + 32;
4331 * No cache invalidation needed here, since the rx_buffer's are
4332 * located in a uncached memory region
4340 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4345 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4346 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4348 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4350 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4351 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4354 static int mvpp2_send(struct udevice *dev, void *packet, int length)
4356 struct mvpp2_port *port = dev_get_priv(dev);
4357 struct mvpp2_tx_queue *txq, *aggr_txq;
4358 struct mvpp2_tx_desc *tx_desc;
4362 txq = port->txqs[0];
4363 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
4365 /* Get a descriptor for the first part of the packet */
4366 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4367 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4368 mvpp2_txdesc_size_set(port, tx_desc, length);
4369 mvpp2_txdesc_offset_set(port, tx_desc,
4370 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
4371 mvpp2_txdesc_dma_addr_set(port, tx_desc,
4372 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
4373 /* First and Last descriptor */
4374 mvpp2_txdesc_cmd_set(port, tx_desc,
4375 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
4376 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
4379 flush_dcache_range((unsigned long)packet,
4380 (unsigned long)packet + ALIGN(length, PKTALIGN));
4382 /* Enable transmit */
4384 mvpp2_aggr_txq_pend_desc_add(port, 1);
4386 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4390 if (timeout++ > 10000) {
4391 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4394 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
4397 /* Enable TXQ drain */
4398 mvpp2_txq_drain(port, txq, 1);
4402 if (timeout++ > 10000) {
4403 printf("timeout: packet not sent\n");
4406 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4409 /* Disable TXQ drain */
4410 mvpp2_txq_drain(port, txq, 0);
4415 static int mvpp2_start(struct udevice *dev)
4417 struct eth_pdata *pdata = dev_get_platdata(dev);
4418 struct mvpp2_port *port = dev_get_priv(dev);
4420 /* Load current MAC address */
4421 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4423 /* Reconfigure parser accept the original MAC address */
4424 mvpp2_prs_update_mac_da(port, port->dev_addr);
4426 mvpp2_port_power_up(port);
4428 mvpp2_open(dev, port);
4433 static void mvpp2_stop(struct udevice *dev)
4435 struct mvpp2_port *port = dev_get_priv(dev);
4437 mvpp2_stop_dev(port);
4438 mvpp2_cleanup_rxqs(port);
4439 mvpp2_cleanup_txqs(port);
4442 static int mvpp2_base_probe(struct udevice *dev)
4444 struct mvpp2 *priv = dev_get_priv(dev);
4445 struct mii_dev *bus;
4450 /* Save hw-version */
4451 priv->hw_version = dev_get_driver_data(dev);
4454 * U-Boot special buffer handling:
4456 * Allocate buffer area for descs and rx_buffers. This is only
4457 * done once for all interfaces. As only one interface can
4458 * be active. Make this area DMA-safe by disabling the D-cache
4461 /* Align buffer area for descs and rx_buffers to 1MiB */
4462 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4463 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
4464 BD_SPACE, DCACHE_OFF);
4466 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4467 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4469 buffer_loc.tx_descs =
4470 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
4471 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4473 buffer_loc.rx_descs =
4474 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
4475 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4477 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4478 buffer_loc.bm_pool[i] =
4479 (unsigned long *)((unsigned long)bd_space + size);
4480 if (priv->hw_version == MVPP21)
4481 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
4483 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
4486 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4487 buffer_loc.rx_buffer[i] =
4488 (unsigned long *)((unsigned long)bd_space + size);
4489 size += RX_BUFFER_SIZE;
4492 /* Clear the complete area so that all descriptors are cleared */
4493 memset(bd_space, 0, size);
4495 /* Save base addresses for later use */
4496 priv->base = (void *)dev_get_addr_index(dev, 0);
4497 if (IS_ERR(priv->base))
4498 return PTR_ERR(priv->base);
4500 if (priv->hw_version == MVPP21) {
4501 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4502 if (IS_ERR(priv->lms_base))
4503 return PTR_ERR(priv->lms_base);
4505 priv->mdio_base = priv->lms_base + MVPP21_SMI;
4507 priv->iface_base = (void *)dev_get_addr_index(dev, 1);
4508 if (IS_ERR(priv->iface_base))
4509 return PTR_ERR(priv->iface_base);
4511 priv->mdio_base = priv->iface_base + MVPP22_SMI;
4514 if (priv->hw_version == MVPP21)
4515 priv->max_port_rxqs = 8;
4517 priv->max_port_rxqs = 32;
4519 /* Finally create and register the MDIO bus driver */
4522 printf("Failed to allocate MDIO bus\n");
4526 bus->read = mpp2_mdio_read;
4527 bus->write = mpp2_mdio_write;
4528 snprintf(bus->name, sizeof(bus->name), dev->name);
4529 bus->priv = (void *)priv;
4532 return mdio_register(bus);
4535 static int mvpp2_probe(struct udevice *dev)
4537 struct mvpp2_port *port = dev_get_priv(dev);
4538 struct mvpp2 *priv = dev_get_priv(dev->parent);
4541 /* Only call the probe function for the parent once */
4542 if (!priv->probe_done) {
4543 err = mvpp2_base_probe(dev->parent);
4544 priv->probe_done = 1;
4547 port->priv = dev_get_priv(dev->parent);
4549 err = phy_info_parse(dev, port);
4554 * We need the port specific io base addresses at this stage, since
4555 * gop_port_init() accesses these registers
4557 if (priv->hw_version == MVPP21) {
4558 int priv_common_regs_num = 2;
4560 port->base = (void __iomem *)dev_get_addr_index(
4561 dev->parent, priv_common_regs_num + port->id);
4562 if (IS_ERR(port->base))
4563 return PTR_ERR(port->base);
4565 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
4567 if (port->id == -1) {
4568 dev_err(&pdev->dev, "missing gop-port-id value\n");
4572 port->base = priv->iface_base + MVPP22_PORT_BASE +
4573 port->gop_id * MVPP22_PORT_OFFSET;
4576 /* Initialize network controller */
4577 err = mvpp2_init(dev, priv);
4579 dev_err(&pdev->dev, "failed to initialize controller\n");
4583 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
4586 static const struct eth_ops mvpp2_ops = {
4587 .start = mvpp2_start,
4593 static struct driver mvpp2_driver = {
4596 .probe = mvpp2_probe,
4598 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4599 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4603 * Use a MISC device to bind the n instances (child nodes) of the
4604 * network base controller in UCLASS_ETH.
4606 static int mvpp2_base_bind(struct udevice *parent)
4608 const void *blob = gd->fdt_blob;
4609 int node = dev_of_offset(parent);
4610 struct uclass_driver *drv;
4611 struct udevice *dev;
4612 struct eth_pdata *plat;
4618 /* Lookup eth driver */
4619 drv = lists_uclass_lookup(UCLASS_ETH);
4621 puts("Cannot find eth driver\n");
4625 base_id_add = base_id;
4627 fdt_for_each_subnode(subnode, blob, node) {
4628 /* Increment base_id for all subnodes, also the disabled ones */
4631 /* Skip disabled ports */
4632 if (!fdtdec_get_is_enabled(blob, subnode))
4635 plat = calloc(1, sizeof(*plat));
4639 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4642 name = calloc(1, 16);
4643 sprintf(name, "mvpp2-%d", id);
4645 /* Create child device UCLASS_ETH and bind it */
4646 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4647 dev_set_of_offset(dev, subnode);
4653 static const struct udevice_id mvpp2_ids[] = {
4655 .compatible = "marvell,armada-375-pp2",
4659 .compatible = "marvell,armada-7k-pp22",
4665 U_BOOT_DRIVER(mvpp2_base) = {
4666 .name = "mvpp2_base",
4668 .of_match = mvpp2_ids,
4669 .bind = mvpp2_base_bind,
4670 .priv_auto_alloc_size = sizeof(struct mvpp2),