git.sur5r.net Git - u-boot/blob - drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <dm/device.h>
  16 #include <generic-phy.h>
  17 #include <phy-sun4i-usb.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/cpu.h>
  22
  23 #define REG_ISCR                        0x00
  24 #define REG_PHYCTL_A10                  0x04
  25 #define REG_PHYBIST                     0x08
  26 #define REG_PHYTUNE                     0x0c
  27 #define REG_PHYCTL_A33                  0x10
  28 #define REG_PHY_OTGCTL                  0x20
  29 #define REG_PMU_UNK1                    0x10
  30
  31 /* Common Control Bits for Both PHYs */
  32 #define PHY_PLL_BW                      0x03
  33 #define PHY_RES45_CAL_EN                0x0c
  34
  35 /* Private Control Bits for Each PHY */
  36 #define PHY_TX_AMPLITUDE_TUNE           0x20
  37 #define PHY_TX_SLEWRATE_TUNE            0x22
  38 #define PHY_DISCON_TH_SEL               0x2a
  39
  40 #define PHYCTL_DATA                     BIT(7)
  41 #define OTGCTL_ROUTE_MUSB               BIT(0)
  42
  43 #define PHY_TX_RATE                     BIT(4)
  44 #define PHY_TX_MAGNITUDE                BIT(2)
  45 #define PHY_TX_AMPLITUDE_LEN            5
  46
  47 #define PHY_RES45_CAL_DATA              BIT(0)
  48 #define PHY_RES45_CAL_LEN               1
  49 #define PHY_DISCON_TH_LEN               2
  50
  51 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  52 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  53 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  54 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  55
  56 /* A83T specific control bits for PHY0 */
  57 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  58 #define PHY_CTL_SIDDQ                   BIT(3)
  59
  60 /* A83T specific control bits for PHY2 HSIC */
  61 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  62 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  63 #define SUNXI_HSIC                      BIT(1)
  64
  65 #define MAX_PHYS                        4
  66
  67 enum sun4i_usb_phy_type {
  68         sun4i_a10_phy,
  69         sun6i_a31_phy,
  70         sun8i_a33_phy,
  71         sun8i_a83t_phy,
  72         sun8i_h3_phy,
  73         sun8i_v3s_phy,
  74         sun50i_a64_phy,
  75 };
  76
  77 struct sun4i_usb_phy_cfg {
  78         int num_phys;
  79         enum sun4i_usb_phy_type type;
  80         u32 disc_thresh;
  81         u8 phyctl_offset;
  82         bool enable_pmu_unk1;
  83         bool phy0_dual_route;
  84 };
  85
  86 struct sun4i_usb_phy_info {
  87         const char *gpio_vbus;
  88         const char *gpio_vbus_det;
  89         const char *gpio_id_det;
  90         int rst_mask;
  91 } phy_info[] = {
  92         {
  93                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
  94                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
  95                 .gpio_id_det = CONFIG_USB0_ID_DET,
  96                 .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
  97         },
  98         {
  99                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
 100                 .gpio_vbus_det = NULL,
 101                 .gpio_id_det = NULL,
 102                 .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 103         },
 104         {
 105                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 106                 .gpio_vbus_det = NULL,
 107                 .gpio_id_det = NULL,
 108 #ifdef CONFIG_MACH_SUN8I_A83T
 109                 .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
 110                              CCM_USB_CTRL_12M_CLK),
 111 #else
 112                 .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
 113 #endif
 114         },
 115         {
 116                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 117                 .gpio_vbus_det = NULL,
 118                 .gpio_id_det = NULL,
 119 #ifdef CONFIG_MACH_SUN6I
 120                 .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
 121 #endif
 122         },
 123 };
 124
 125 struct sun4i_usb_phy_plat {
 126         void __iomem *pmu;
 127         int power_on_count;
 128         int gpio_vbus;
 129         int gpio_vbus_det;
 130         int gpio_id_det;
 131         int rst_mask;
 132         int id;
 133 };
 134
 135 struct sun4i_usb_phy_data {
 136         void __iomem *base;
 137         struct sunxi_ccm_reg *ccm;
 138         const struct sun4i_usb_phy_cfg *cfg;
 139         struct sun4i_usb_phy_plat *usb_phy;
 140 };
 141
 142 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 143
 144 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 145 {
 146         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 147         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 148         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 149         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 150         int i;
 151
 152         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 153                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 154                 writel(0, phyctl);
 155         }
 156
 157         for (i = 0; i < len; i++) {
 158                 temp = readl(phyctl);
 159
 160                 /* clear the address portion */
 161                 temp &= ~(0xff << 8);
 162
 163                 /* set the address */
 164                 temp |= ((addr + i) << 8);
 165                 writel(temp, phyctl);
 166
 167                 /* set the data bit and clear usbc bit*/
 168                 temp = readb(phyctl);
 169                 if (data & 0x1)
 170                         temp |= PHYCTL_DATA;
 171                 else
 172                         temp &= ~PHYCTL_DATA;
 173                 temp &= ~usbc_bit;
 174                 writeb(temp, phyctl);
 175
 176                 /* pulse usbc_bit */
 177                 temp = readb(phyctl);
 178                 temp |= usbc_bit;
 179                 writeb(temp, phyctl);
 180
 181                 temp = readb(phyctl);
 182                 temp &= ~usbc_bit;
 183                 writeb(temp, phyctl);
 184
 185                 data >>= 1;
 186         }
 187 }
 188
 189 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 190 {
 191         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 192         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 193         u32 bits, reg_value;
 194
 195         if (!usb_phy->pmu)
 196                 return;
 197
 198         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 199                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 200
 201         /* A83T USB2 is HSIC */
 202         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 203                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 204                         SUNXI_HSIC;
 205
 206         reg_value = readl(usb_phy->pmu);
 207
 208         if (enable)
 209                 reg_value |= bits;
 210         else
 211                 reg_value &= ~bits;
 212
 213         writel(reg_value, usb_phy->pmu);
 214 }
 215
 216 static int sun4i_usb_phy_power_on(struct phy *phy)
 217 {
 218         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 219         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 220
 221         if (initial_usb_scan_delay) {
 222                 mdelay(initial_usb_scan_delay);
 223                 initial_usb_scan_delay = 0;
 224         }
 225
 226         usb_phy->power_on_count++;
 227         if (usb_phy->power_on_count != 1)
 228                 return 0;
 229
 230         if (usb_phy->gpio_vbus >= 0)
 231                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 232
 233         return 0;
 234 }
 235
 236 static int sun4i_usb_phy_power_off(struct phy *phy)
 237 {
 238         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 239         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 240
 241         usb_phy->power_on_count--;
 242         if (usb_phy->power_on_count != 0)
 243                 return 0;
 244
 245         if (usb_phy->gpio_vbus >= 0)
 246                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 247
 248         return 0;
 249 }
 250
 251 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 252 {
 253         u32 regval;
 254
 255         regval = readl(data->base + REG_PHY_OTGCTL);
 256         if (!id_det) {
 257                 /* Host mode. Route phy0 to EHCI/OHCI */
 258                 regval &= ~OTGCTL_ROUTE_MUSB;
 259         } else {
 260                 /* Peripheral mode. Route phy0 to MUSB */
 261                 regval |= OTGCTL_ROUTE_MUSB;
 262         }
 263         writel(regval, data->base + REG_PHY_OTGCTL);
 264 }
 265
 266 static int sun4i_usb_phy_init(struct phy *phy)
 267 {
 268         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 269         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 270         u32 val;
 271
 272         setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 273
 274         if (data->cfg->type == sun8i_a83t_phy) {
 275                 if (phy->id == 0) {
 276                         val = readl(data->base + data->cfg->phyctl_offset);
 277                         val |= PHY_CTL_VBUSVLDEXT;
 278                         val &= ~PHY_CTL_SIDDQ;
 279                         writel(val, data->base + data->cfg->phyctl_offset);
 280                 }
 281         } else {
 282                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 283                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 284                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 285                 }
 286
 287                 if (usb_phy->id == 0)
 288                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 289                                             PHY_RES45_CAL_DATA,
 290                                             PHY_RES45_CAL_LEN);
 291
 292                 /* Adjust PHY's magnitude and rate */
 293                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 294                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 295                                     PHY_TX_AMPLITUDE_LEN);
 296
 297                 /* Disconnect threshold adjustment */
 298                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 299                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 300         }
 301
 302         if (usb_phy->id != 0)
 303                 sun4i_usb_phy_passby(phy, true);
 304
 305         sun4i_usb_phy0_reroute(data, true);
 306
 307         return 0;
 308 }
 309
 310 static int sun4i_usb_phy_exit(struct phy *phy)
 311 {
 312         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 313         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 314
 315         if (phy->id == 0) {
 316                 if (data->cfg->type == sun8i_a83t_phy) {
 317                         void __iomem *phyctl = data->base +
 318                                 data->cfg->phyctl_offset;
 319
 320                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 321                 }
 322         }
 323
 324         sun4i_usb_phy_passby(phy, false);
 325
 326         clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 327
 328         return 0;
 329 }
 330
 331 static int sun4i_usb_phy_xlate(struct phy *phy,
 332                                struct ofnode_phandle_args *args)
 333 {
 334         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 335
 336         if (args->args_count >= data->cfg->num_phys)
 337                 return -EINVAL;
 338
 339         if (args->args_count)
 340                 phy->id = args->args[0];
 341         else
 342                 phy->id = 0;
 343
 344         debug("%s: phy_id = %ld\n", __func__, phy->id);
 345         return 0;
 346 }
 347
 348 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 349 {
 350         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 351         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 352         int err, retries = 3;
 353
 354         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 355
 356         if (usb_phy->gpio_vbus_det < 0)
 357                 return usb_phy->gpio_vbus_det;
 358
 359         err = gpio_get_value(usb_phy->gpio_vbus_det);
 360         /*
 361          * Vbus may have been provided by the board and just been turned of
 362          * some milliseconds ago on reset, what we're measuring then is a
 363          * residual charge on Vbus, sleep a bit and try again.
 364          */
 365         while (err > 0 && retries--) {
 366                 mdelay(100);
 367                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 368         }
 369
 370         return err;
 371 }
 372
 373 int sun4i_usb_phy_id_detect(struct phy *phy)
 374 {
 375         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 376         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 377
 378         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 379
 380         if (usb_phy->gpio_id_det < 0)
 381                 return usb_phy->gpio_id_det;
 382
 383         return gpio_get_value(usb_phy->gpio_id_det);
 384 }
 385
 386 static struct phy_ops sun4i_usb_phy_ops = {
 387         .of_xlate = sun4i_usb_phy_xlate,
 388         .init = sun4i_usb_phy_init,
 389         .power_on = sun4i_usb_phy_power_on,
 390         .power_off = sun4i_usb_phy_power_off,
 391         .exit = sun4i_usb_phy_exit,
 392 };
 393
 394 static int sun4i_usb_phy_probe(struct udevice *dev)
 395 {
 396         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 397         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 398         int i, ret;
 399
 400         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 401         if (!data->cfg)
 402                 return -EINVAL;
 403
 404         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 405         if (IS_ERR(data->base))
 406                 return PTR_ERR(data->base);
 407
 408         data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 409         if (IS_ERR(data->ccm))
 410                 return PTR_ERR(data->ccm);
 411
 412         data->usb_phy = plat;
 413         for (i = 0; i < data->cfg->num_phys; i++) {
 414                 struct sun4i_usb_phy_plat *phy = &plat[i];
 415                 struct sun4i_usb_phy_info *info = &phy_info[i];
 416                 char name[16];
 417
 418                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 419                 if (phy->gpio_vbus >= 0) {
 420                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 421                         if (ret)
 422                                 return ret;
 423                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 424                         if (ret)
 425                                 return ret;
 426                 }
 427
 428                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 429                 if (phy->gpio_vbus_det >= 0) {
 430                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 431                         if (ret)
 432                                 return ret;
 433                         ret = gpio_direction_input(phy->gpio_vbus_det);
 434                         if (ret)
 435                                 return ret;
 436                 }
 437
 438                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 439                 if (phy->gpio_id_det >= 0) {
 440                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 441                         if (ret)
 442                                 return ret;
 443                         ret = gpio_direction_input(phy->gpio_id_det);
 444                         if (ret)
 445                                 return ret;
 446                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 447                 }
 448
 449                 if (i || data->cfg->phy0_dual_route) {
 450                         snprintf(name, sizeof(name), "pmu%d", i);
 451                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 452                         if (IS_ERR(phy->pmu))
 453                                 return PTR_ERR(phy->pmu);
 454                 }
 455
 456                 phy->id = i;
 457                 phy->rst_mask = info->rst_mask;
 458         };
 459
 460         setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 461
 462         debug("Allwinner Sun4I USB PHY driver loaded\n");
 463         return 0;
 464 }
 465
 466 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 467         .num_phys = 3,
 468         .type = sun4i_a10_phy,
 469         .disc_thresh = 3,
 470         .phyctl_offset = REG_PHYCTL_A10,
 471         .enable_pmu_unk1 = false,
 472 };
 473
 474 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 475         .num_phys = 2,
 476         .type = sun4i_a10_phy,
 477         .disc_thresh = 2,
 478         .phyctl_offset = REG_PHYCTL_A10,
 479         .enable_pmu_unk1 = false,
 480 };
 481
 482 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 483         .num_phys = 3,
 484         .type = sun6i_a31_phy,
 485         .disc_thresh = 3,
 486         .phyctl_offset = REG_PHYCTL_A10,
 487         .enable_pmu_unk1 = false,
 488 };
 489
 490 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 491         .num_phys = 3,
 492         .type = sun4i_a10_phy,
 493         .disc_thresh = 2,
 494         .phyctl_offset = REG_PHYCTL_A10,
 495         .enable_pmu_unk1 = false,
 496 };
 497
 498 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 499         .num_phys = 2,
 500         .type = sun8i_a33_phy,
 501         .disc_thresh = 3,
 502         .phyctl_offset = REG_PHYCTL_A33,
 503         .enable_pmu_unk1 = false,
 504 };
 505
 506 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 507         .num_phys = 3,
 508         .type = sun8i_a83t_phy,
 509         .phyctl_offset = REG_PHYCTL_A33,
 510 };
 511
 512 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 513         .num_phys = 4,
 514         .type = sun8i_h3_phy,
 515         .disc_thresh = 3,
 516         .phyctl_offset = REG_PHYCTL_A33,
 517         .enable_pmu_unk1 = true,
 518         .phy0_dual_route = true,
 519 };
 520
 521 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 522         .num_phys = 1,
 523         .type = sun8i_v3s_phy,
 524         .disc_thresh = 3,
 525         .phyctl_offset = REG_PHYCTL_A33,
 526         .enable_pmu_unk1 = true,
 527         .phy0_dual_route = true,
 528 };
 529
 530 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 531         .num_phys = 2,
 532         .type = sun50i_a64_phy,
 533         .disc_thresh = 3,
 534         .phyctl_offset = REG_PHYCTL_A33,
 535         .enable_pmu_unk1 = true,
 536         .phy0_dual_route = true,
 537 };
 538
 539 static const struct udevice_id sun4i_usb_phy_ids[] = {
 540         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 541         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 542         { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 543         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 544         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 545         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 546         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 547         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 548         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 549         { }
 550 };
 551
 552 U_BOOT_DRIVER(sun4i_usb_phy) = {
 553         .name   = "sun4i_usb_phy",
 554         .id     = UCLASS_PHY,
 555         .of_match = sun4i_usb_phy_ids,
 556         .ops = &sun4i_usb_phy_ops,
 557         .probe = sun4i_usb_phy_probe,
 558         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 559         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 560 };