git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3036.c

   1 /*
   2  * Pinctrl driver for Rockchip 3036 SoCs
   3  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/grf_rk3036.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/periph.h>
  17 #include <dm/pinctrl.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /* GRF_GPIO0A_IOMUX */
  22 enum {
  23         GPIO0A3_SHIFT           = 6,
  24         GPIO0A3_MASK            = 1 << GPIO0A3_SHIFT,
  25         GPIO0A3_GPIO            = 0,
  26         GPIO0A3_I2C1_SDA,
  27
  28         GPIO0A2_SHIFT           = 4,
  29         GPIO0A2_MASK            = 1 << GPIO0A2_SHIFT,
  30         GPIO0A2_GPIO            = 0,
  31         GPIO0A2_I2C1_SCL,
  32
  33         GPIO0A1_SHIFT           = 2,
  34         GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
  35         GPIO0A1_GPIO            = 0,
  36         GPIO0A1_I2C0_SDA,
  37         GPIO0A1_PWM2,
  38
  39         GPIO0A0_SHIFT           = 0,
  40         GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
  41         GPIO0A0_GPIO            = 0,
  42         GPIO0A0_I2C0_SCL,
  43         GPIO0A0_PWM1,
  44 };
  45
  46 /* GRF_GPIO0B_IOMUX */
  47 enum {
  48         GPIO0B6_SHIFT           = 12,
  49         GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
  50         GPIO0B6_GPIO            = 0,
  51         GPIO0B6_MMC1_D3,
  52         GPIO0B6_I2S1_SCLK,
  53
  54         GPIO0B5_SHIFT           = 10,
  55         GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
  56         GPIO0B5_GPIO            = 0,
  57         GPIO0B5_MMC1_D2,
  58         GPIO0B5_I2S1_SDI,
  59
  60         GPIO0B4_SHIFT           = 8,
  61         GPIO0B4_MASK            = 3 << GPIO0B4_SHIFT,
  62         GPIO0B4_GPIO            = 0,
  63         GPIO0B4_MMC1_D1,
  64         GPIO0B4_I2S1_LRCKTX,
  65
  66         GPIO0B3_SHIFT           = 6,
  67         GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
  68         GPIO0B3_GPIO            = 0,
  69         GPIO0B3_MMC1_D0,
  70         GPIO0B3_I2S1_LRCKRX,
  71
  72         GPIO0B1_SHIFT           = 2,
  73         GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
  74         GPIO0B1_GPIO            = 0,
  75         GPIO0B1_MMC1_CLKOUT,
  76         GPIO0B1_I2S1_MCLK,
  77
  78         GPIO0B0_SHIFT           = 0,
  79         GPIO0B0_MASK            = 3,
  80         GPIO0B0_GPIO            = 0,
  81         GPIO0B0_MMC1_CMD,
  82         GPIO0B0_I2S1_SDO,
  83 };
  84
  85 /* GRF_GPIO0C_IOMUX */
  86 enum {
  87         GPIO0C4_SHIFT           = 8,
  88         GPIO0C4_MASK            = 1 << GPIO0C4_SHIFT,
  89         GPIO0C4_GPIO            = 0,
  90         GPIO0C4_DRIVE_VBUS,
  91
  92         GPIO0C3_SHIFT           = 6,
  93         GPIO0C3_MASK            = 1 << GPIO0C3_SHIFT,
  94         GPIO0C3_GPIO            = 0,
  95         GPIO0C3_UART0_CTSN,
  96
  97         GPIO0C2_SHIFT           = 4,
  98         GPIO0C2_MASK            = 1 << GPIO0C2_SHIFT,
  99         GPIO0C2_GPIO            = 0,
 100         GPIO0C2_UART0_RTSN,
 101
 102         GPIO0C1_SHIFT           = 2,
 103         GPIO0C1_MASK            = 1 << GPIO0C1_SHIFT,
 104         GPIO0C1_GPIO            = 0,
 105         GPIO0C1_UART0_SIN,
 106
 107
 108         GPIO0C0_SHIFT           = 0,
 109         GPIO0C0_MASK            = 1 << GPIO0C0_SHIFT,
 110         GPIO0C0_GPIO            = 0,
 111         GPIO0C0_UART0_SOUT,
 112 };
 113
 114 /* GRF_GPIO0D_IOMUX */
 115 enum {
 116         GPIO0D4_SHIFT           = 8,
 117         GPIO0D4_MASK            = 1 << GPIO0D4_SHIFT,
 118         GPIO0D4_GPIO            = 0,
 119         GPIO0D4_SPDIF,
 120
 121         GPIO0D3_SHIFT           = 6,
 122         GPIO0D3_MASK            = 1 << GPIO0D3_SHIFT,
 123         GPIO0D3_GPIO            = 0,
 124         GPIO0D3_PWM3,
 125
 126         GPIO0D2_SHIFT           = 4,
 127         GPIO0D2_MASK            = 1 << GPIO0D2_SHIFT,
 128         GPIO0D2_GPIO            = 0,
 129         GPIO0D2_PWM0,
 130 };
 131
 132 /* GRF_GPIO1A_IOMUX */
 133 enum {
 134         GPIO1A5_SHIFT           = 10,
 135         GPIO1A5_MASK            = 1 << GPIO1A5_SHIFT,
 136         GPIO1A5_GPIO            = 0,
 137         GPIO1A5_I2S_SDI,
 138
 139         GPIO1A4_SHIFT           = 8,
 140         GPIO1A4_MASK            = 1 << GPIO1A4_SHIFT,
 141         GPIO1A4_GPIO            = 0,
 142         GPIO1A4_I2S_SD0,
 143
 144         GPIO1A3_SHIFT           = 6,
 145         GPIO1A3_MASK            = 1 << GPIO1A3_SHIFT,
 146         GPIO1A3_GPIO            = 0,
 147         GPIO1A3_I2S_LRCKTX,
 148
 149         GPIO1A2_SHIFT           = 4,
 150         GPIO1A2_MASK            = 3 << GPIO1A2_SHIFT,
 151         GPIO1A2_GPIO            = 0,
 152         GPIO1A2_I2S_LRCKRX,
 153         GPIO1A2_PWM1_0,
 154
 155         GPIO1A1_SHIFT           = 2,
 156         GPIO1A1_MASK            = 1 << GPIO1A1_SHIFT,
 157         GPIO1A1_GPIO            = 0,
 158         GPIO1A1_I2S_SCLK,
 159
 160         GPIO1A0_SHIFT           = 0,
 161         GPIO1A0_MASK            = 1 << GPIO1A0_SHIFT,
 162         GPIO1A0_GPIO            = 0,
 163         GPIO1A0_I2S_MCLK,
 164
 165 };
 166
 167 /* GRF_GPIO1B_IOMUX */
 168 enum {
 169         GPIO1B7_SHIFT           = 14,
 170         GPIO1B7_MASK            = 1 << GPIO1B7_SHIFT,
 171         GPIO1B7_GPIO            = 0,
 172         GPIO1B7_MMC0_CMD,
 173
 174         GPIO1B3_SHIFT           = 6,
 175         GPIO1B3_MASK            = 1 << GPIO1B3_SHIFT,
 176         GPIO1B3_GPIO            = 0,
 177         GPIO1B3_HDMI_HPD,
 178
 179         GPIO1B2_SHIFT           = 4,
 180         GPIO1B2_MASK            = 1 << GPIO1B2_SHIFT,
 181         GPIO1B2_GPIO            = 0,
 182         GPIO1B2_HDMI_SCL,
 183
 184         GPIO1B1_SHIFT           = 2,
 185         GPIO1B1_MASK            = 1 << GPIO1B1_SHIFT,
 186         GPIO1B1_GPIO            = 0,
 187         GPIO1B1_HDMI_SDA,
 188
 189         GPIO1B0_SHIFT           = 0,
 190         GPIO1B0_MASK            = 1 << GPIO1B0_SHIFT,
 191         GPIO1B0_GPIO            = 0,
 192         GPIO1B0_HDMI_CEC,
 193 };
 194
 195 /* GRF_GPIO1C_IOMUX */
 196 enum {
 197         GPIO1C5_SHIFT           = 10,
 198         GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
 199         GPIO1C5_GPIO            = 0,
 200         GPIO1C5_MMC0_D3,
 201         GPIO1C5_JTAG_TMS,
 202
 203         GPIO1C4_SHIFT           = 8,
 204         GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
 205         GPIO1C4_GPIO            = 0,
 206         GPIO1C4_MMC0_D2,
 207         GPIO1C4_JTAG_TCK,
 208
 209         GPIO1C3_SHIFT           = 6,
 210         GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
 211         GPIO1C3_GPIO            = 0,
 212         GPIO1C3_MMC0_D1,
 213         GPIO1C3_UART2_SOUT,
 214
 215         GPIO1C2_SHIFT           = 4,
 216         GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT ,
 217         GPIO1C2_GPIO            = 0,
 218         GPIO1C2_MMC0_D0,
 219         GPIO1C2_UART2_SIN,
 220
 221         GPIO1C1_SHIFT           = 2,
 222         GPIO1C1_MASK            = 1 << GPIO1C1_SHIFT,
 223         GPIO1C1_GPIO            = 0,
 224         GPIO1C1_MMC0_DETN,
 225
 226         GPIO1C0_SHIFT           = 0,
 227         GPIO1C0_MASK            = 1 << GPIO1C0_SHIFT,
 228         GPIO1C0_GPIO            = 0,
 229         GPIO1C0_MMC0_CLKOUT,
 230 };
 231
 232 /* GRF_GPIO1D_IOMUX */
 233 enum {
 234         GPIO1D7_SHIFT           = 14,
 235         GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
 236         GPIO1D7_GPIO            = 0,
 237         GPIO1D7_NAND_D7,
 238         GPIO1D7_EMMC_D7,
 239         GPIO1D7_SPI_CSN1,
 240
 241         GPIO1D6_SHIFT           = 12,
 242         GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
 243         GPIO1D6_GPIO            = 0,
 244         GPIO1D6_NAND_D6,
 245         GPIO1D6_EMMC_D6,
 246         GPIO1D6_SPI_CSN0,
 247
 248         GPIO1D5_SHIFT           = 10,
 249         GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
 250         GPIO1D5_GPIO            = 0,
 251         GPIO1D5_NAND_D5,
 252         GPIO1D5_EMMC_D5,
 253         GPIO1D5_SPI_TXD,
 254
 255         GPIO1D4_SHIFT           = 8,
 256         GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
 257         GPIO1D4_GPIO            = 0,
 258         GPIO1D4_NAND_D4,
 259         GPIO1D4_EMMC_D4,
 260         GPIO1D4_SPI_RXD,
 261
 262         GPIO1D3_SHIFT           = 6,
 263         GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
 264         GPIO1D3_GPIO            = 0,
 265         GPIO1D3_NAND_D3,
 266         GPIO1D3_EMMC_D3,
 267         GPIO1D3_SFC_SIO3,
 268
 269         GPIO1D2_SHIFT           = 4,
 270         GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
 271         GPIO1D2_GPIO            = 0,
 272         GPIO1D2_NAND_D2,
 273         GPIO1D2_EMMC_D2,
 274         GPIO1D2_SFC_SIO2,
 275
 276         GPIO1D1_SHIFT           = 2,
 277         GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
 278         GPIO1D1_GPIO            = 0,
 279         GPIO1D1_NAND_D1,
 280         GPIO1D1_EMMC_D1,
 281         GPIO1D1_SFC_SIO1,
 282
 283         GPIO1D0_SHIFT           = 0,
 284         GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
 285         GPIO1D0_GPIO            = 0,
 286         GPIO1D0_NAND_D0,
 287         GPIO1D0_EMMC_D0,
 288         GPIO1D0_SFC_SIO0,
 289 };
 290
 291 /* GRF_GPIO2A_IOMUX */
 292 enum {
 293         GPIO2A7_SHIFT           = 14,
 294         GPIO2A7_MASK            = 1 << GPIO2A7_SHIFT,
 295         GPIO2A7_GPIO            = 0,
 296         GPIO2A7_TESTCLK_OUT,
 297
 298         GPIO2A6_SHIFT           = 12,
 299         GPIO2A6_MASK            = 1 << GPIO2A6_SHIFT,
 300         GPIO2A6_GPIO            = 0,
 301         GPIO2A6_NAND_CS0,
 302
 303         GPIO2A4_SHIFT           = 8,
 304         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 305         GPIO2A4_GPIO            = 0,
 306         GPIO2A4_NAND_RDY,
 307         GPIO2A4_EMMC_CMD,
 308         GPIO2A3_SFC_CLK,
 309
 310         GPIO2A3_SHIFT           = 6,
 311         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 312         GPIO2A3_GPIO            = 0,
 313         GPIO2A3_NAND_RDN,
 314         GPIO2A4_SFC_CSN1,
 315
 316         GPIO2A2_SHIFT           = 4,
 317         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 318         GPIO2A2_GPIO            = 0,
 319         GPIO2A2_NAND_WRN,
 320         GPIO2A4_SFC_CSN0,
 321
 322         GPIO2A1_SHIFT           = 2,
 323         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 324         GPIO2A1_GPIO            = 0,
 325         GPIO2A1_NAND_CLE,
 326         GPIO2A1_EMMC_CLKOUT,
 327
 328         GPIO2A0_SHIFT           = 0,
 329         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 330         GPIO2A0_GPIO            = 0,
 331         GPIO2A0_NAND_ALE,
 332         GPIO2A0_SPI_CLK,
 333 };
 334
 335 /* GRF_GPIO2B_IOMUX */
 336 enum {
 337         GPIO2B7_SHIFT           = 14,
 338         GPIO2B7_MASK            = 1 << GPIO2B7_SHIFT,
 339         GPIO2B7_GPIO            = 0,
 340         GPIO2B7_MAC_RXER,
 341
 342         GPIO2B6_SHIFT           = 12,
 343         GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
 344         GPIO2B6_GPIO            = 0,
 345         GPIO2B6_MAC_CLKOUT,
 346         GPIO2B6_MAC_CLKIN,
 347
 348         GPIO2B5_SHIFT           = 10,
 349         GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
 350         GPIO2B5_GPIO            = 0,
 351         GPIO2B5_MAC_TXEN,
 352
 353         GPIO2B4_SHIFT           = 8,
 354         GPIO2B4_MASK            = 1 << GPIO2B4_SHIFT,
 355         GPIO2B4_GPIO            = 0,
 356         GPIO2B4_MAC_MDIO,
 357
 358         GPIO2B2_SHIFT           = 4,
 359         GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
 360         GPIO2B2_GPIO            = 0,
 361         GPIO2B2_MAC_CRS,
 362 };
 363
 364 /* GRF_GPIO2C_IOMUX */
 365 enum {
 366         GPIO2C7_SHIFT           = 14,
 367         GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
 368         GPIO2C7_GPIO            = 0,
 369         GPIO2C7_UART1_SOUT,
 370         GPIO2C7_TESTCLK_OUT1,
 371
 372         GPIO2C6_SHIFT           = 12,
 373         GPIO2C6_MASK            = 1 << GPIO2C6_SHIFT,
 374         GPIO2C6_GPIO            = 0,
 375         GPIO2C6_UART1_SIN,
 376
 377         GPIO2C5_SHIFT           = 10,
 378         GPIO2C5_MASK            = 1 << GPIO2C5_SHIFT,
 379         GPIO2C5_GPIO            = 0,
 380         GPIO2C5_I2C2_SCL,
 381
 382         GPIO2C4_SHIFT           = 8,
 383         GPIO2C4_MASK            = 1 << GPIO2C4_SHIFT,
 384         GPIO2C4_GPIO            = 0,
 385         GPIO2C4_I2C2_SDA,
 386
 387         GPIO2C3_SHIFT           = 6,
 388         GPIO2C3_MASK            = 1 << GPIO2C3_SHIFT,
 389         GPIO2C3_GPIO            = 0,
 390         GPIO2C3_MAC_TXD0,
 391
 392         GPIO2C2_SHIFT           = 4,
 393         GPIO2C2_MASK            = 1 << GPIO2C2_SHIFT,
 394         GPIO2C2_GPIO            = 0,
 395         GPIO2C2_MAC_TXD1,
 396
 397         GPIO2C1_SHIFT           = 2,
 398         GPIO2C1_MASK            = 1 << GPIO2C1_SHIFT,
 399         GPIO2C1_GPIO            = 0,
 400         GPIO2C1_MAC_RXD0,
 401
 402         GPIO2C0_SHIFT           = 0,
 403         GPIO2C0_MASK            = 1 << GPIO2C0_SHIFT,
 404         GPIO2C0_GPIO            = 0,
 405         GPIO2C0_MAC_RXD1,
 406 };
 407
 408 /* GRF_GPIO2D_IOMUX */
 409 enum {
 410         GPIO2D6_SHIFT           = 12,
 411         GPIO2D6_MASK            = 1 << GPIO2D6_SHIFT,
 412         GPIO2D6_GPIO            = 0,
 413         GPIO2D6_I2S_SDO1,
 414
 415         GPIO2D5_SHIFT           = 10,
 416         GPIO2D5_MASK            = 1 << GPIO2D5_SHIFT,
 417         GPIO2D5_GPIO            = 0,
 418         GPIO2D5_I2S_SDO2,
 419
 420         GPIO2D4_SHIFT           = 8,
 421         GPIO2D4_MASK            = 1 << GPIO2D4_SHIFT,
 422         GPIO2D4_GPIO            = 0,
 423         GPIO2D4_I2S_SDO3,
 424
 425         GPIO2D1_SHIFT           = 2,
 426         GPIO2D1_MASK            = 1 << GPIO2D1_SHIFT,
 427         GPIO2D1_GPIO            = 0,
 428         GPIO2D1_MAC_MDC,
 429 };
 430
 431 struct rk3036_pinctrl_priv {
 432         struct rk3036_grf *grf;
 433 };
 434
 435 static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
 436 {
 437         switch (pwm_id) {
 438         case PERIPH_ID_PWM0:
 439                 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
 440                              GPIO0D2_PWM0 << GPIO0D2_SHIFT);
 441                 break;
 442         case PERIPH_ID_PWM1:
 443                 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK,
 444                              GPIO0A0_PWM1 << GPIO0A0_SHIFT);
 445                 break;
 446         case PERIPH_ID_PWM2:
 447                 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK,
 448                              GPIO0A1_PWM2 << GPIO0A1_SHIFT);
 449                 break;
 450         case PERIPH_ID_PWM3:
 451                 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK,
 452                              GPIO0D3_PWM3 << GPIO0D3_SHIFT);
 453                 break;
 454         default:
 455                 debug("pwm id = %d iomux error!\n", pwm_id);
 456                 break;
 457         }
 458 }
 459
 460 static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
 461 {
 462         switch (i2c_id) {
 463         case PERIPH_ID_I2C0:
 464                 rk_clrsetreg(&grf->gpio0a_iomux,
 465                              GPIO0A1_MASK | GPIO0A0_MASK,
 466                              GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
 467                              GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
 468
 469                 break;
 470         case PERIPH_ID_I2C1:
 471                 rk_clrsetreg(&grf->gpio0a_iomux,
 472                              GPIO0A3_MASK | GPIO0A2_MASK,
 473                              GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
 474                              GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
 475                 break;
 476         case PERIPH_ID_I2C2:
 477                 rk_clrsetreg(&grf->gpio2c_iomux,
 478                              GPIO2C5_MASK | GPIO2C4_MASK,
 479                              GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
 480                              GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
 481
 482                 break;
 483         }
 484 }
 485
 486 static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
 487 {
 488         switch (cs) {
 489         case 0:
 490                 rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK,
 491                              GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
 492                 break;
 493         case 1:
 494                 rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK,
 495                              GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
 496                 break;
 497         }
 498         rk_clrsetreg(&grf->gpio1d_iomux,
 499                      GPIO1D5_MASK | GPIO1D4_MASK,
 500                      GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
 501                      GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
 502
 503         rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK,
 504                      GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
 505 }
 506
 507 static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
 508 {
 509         switch (uart_id) {
 510         case PERIPH_ID_UART0:
 511                 rk_clrsetreg(&grf->gpio0c_iomux,
 512                              GPIO0C3_MASK | GPIO0C2_MASK |
 513                              GPIO0C1_MASK |  GPIO0C0_MASK,
 514                              GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
 515                              GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
 516                              GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
 517                              GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
 518                 break;
 519         case PERIPH_ID_UART1:
 520                 rk_clrsetreg(&grf->gpio2c_iomux,
 521                              GPIO2C7_MASK | GPIO2C6_MASK,
 522                              GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
 523                              GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
 524                 break;
 525         case PERIPH_ID_UART2:
 526                 rk_clrsetreg(&grf->gpio1c_iomux,
 527                              GPIO1C3_MASK | GPIO1C2_MASK,
 528                              GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 529                              GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
 530                 break;
 531         }
 532 }
 533
 534 static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
 535 {
 536         switch (mmc_id) {
 537         case PERIPH_ID_EMMC:
 538                 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
 539                              GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
 540                              GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
 541                              GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
 542                              GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
 543                              GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
 544                              GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
 545                              GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
 546                              GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
 547                 rk_clrsetreg(&grf->gpio2a_iomux,
 548                              GPIO2A4_MASK | GPIO2A1_MASK,
 549                              GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
 550                              GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
 551                 break;
 552         case PERIPH_ID_SDCARD:
 553                 rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
 554                              GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
 555                              GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
 556                              GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
 557                              GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
 558                              GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
 559                              GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
 560                 break;
 561         }
 562 }
 563
 564 static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
 565 {
 566         struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
 567
 568         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 569         switch (func) {
 570         case PERIPH_ID_PWM0:
 571         case PERIPH_ID_PWM1:
 572         case PERIPH_ID_PWM2:
 573         case PERIPH_ID_PWM3:
 574                 pinctrl_rk3036_pwm_config(priv->grf, func);
 575                 break;
 576         case PERIPH_ID_I2C0:
 577         case PERIPH_ID_I2C1:
 578         case PERIPH_ID_I2C2:
 579                 pinctrl_rk3036_i2c_config(priv->grf, func);
 580                 break;
 581         case PERIPH_ID_SPI0:
 582                 pinctrl_rk3036_spi_config(priv->grf, flags);
 583                 break;
 584         case PERIPH_ID_UART0:
 585         case PERIPH_ID_UART1:
 586         case PERIPH_ID_UART2:
 587                 pinctrl_rk3036_uart_config(priv->grf, func);
 588                 break;
 589         case PERIPH_ID_SDMMC0:
 590         case PERIPH_ID_SDMMC1:
 591                 pinctrl_rk3036_sdmmc_config(priv->grf, func);
 592                 break;
 593         default:
 594                 return -EINVAL;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
 601                                         struct udevice *periph)
 602 {
 603         u32 cell[3];
 604         int ret;
 605
 606         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 607         if (ret < 0)
 608                 return -EINVAL;
 609
 610         switch (cell[1]) {
 611         case 14:
 612                 return PERIPH_ID_SDCARD;
 613         case 16:
 614                 return PERIPH_ID_EMMC;
 615         case 20:
 616                 return PERIPH_ID_UART0;
 617         case 21:
 618                 return PERIPH_ID_UART1;
 619         case 22:
 620                 return PERIPH_ID_UART2;
 621         case 23:
 622                 return PERIPH_ID_SPI0;
 623         case 24:
 624                 return PERIPH_ID_I2C0;
 625         case 25:
 626                 return PERIPH_ID_I2C1;
 627         case 26:
 628                 return PERIPH_ID_I2C2;
 629         case 30:
 630                 return PERIPH_ID_PWM0;
 631         }
 632         return -ENOENT;
 633 }
 634
 635 static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
 636                                            struct udevice *periph)
 637 {
 638         int func;
 639
 640         func = rk3036_pinctrl_get_periph_id(dev, periph);
 641         if (func < 0)
 642                 return func;
 643         return rk3036_pinctrl_request(dev, func, 0);
 644 }
 645
 646 static struct pinctrl_ops rk3036_pinctrl_ops = {
 647         .set_state_simple       = rk3036_pinctrl_set_state_simple,
 648         .request        = rk3036_pinctrl_request,
 649         .get_periph_id  = rk3036_pinctrl_get_periph_id,
 650 };
 651
 652 static int rk3036_pinctrl_probe(struct udevice *dev)
 653 {
 654         struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
 655
 656         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 657         debug("%s: grf=%p\n", __func__, priv->grf);
 658         return 0;
 659 }
 660
 661 static const struct udevice_id rk3036_pinctrl_ids[] = {
 662         { .compatible = "rockchip,rk3036-pinctrl" },
 663         { }
 664 };
 665
 666 U_BOOT_DRIVER(pinctrl_rk3036) = {
 667         .name           = "pinctrl_rk3036",
 668         .id             = UCLASS_PINCTRL,
 669         .of_match       = rk3036_pinctrl_ids,
 670         .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
 671         .ops            = &rk3036_pinctrl_ops,
 672         .bind           = dm_scan_fdt_dev,
 673         .probe          = rk3036_pinctrl_probe,
 674 };