git.sur5r.net Git - u-boot/blob - drivers/qe/uec.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include "common.h"
  23 #include "net.h"
  24 #include "malloc.h"
  25 #include "asm/errno.h"
  26 #include "asm/io.h"
  27 #include "asm/immap_qe.h"
  28 #include "qe.h"
  29 #include "uccf.h"
  30 #include "uec.h"
  31 #include "uec_phy.h"
  32
  33 #if defined(CONFIG_QE)
  34
  35 #ifdef CONFIG_UEC_ETH1
  36 static uec_info_t eth1_uec_info = {
  37         .uf_info                = {
  38                 .ucc_num        = CFG_UEC1_UCC_NUM,
  39                 .rx_clock       = CFG_UEC1_RX_CLK,
  40                 .tx_clock       = CFG_UEC1_TX_CLK,
  41                 .eth_type       = CFG_UEC1_ETH_TYPE,
  42         },
  43 #if (CFG_UEC1_ETH_TYPE == FAST_ETH)
  44         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  45         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  46 #else
  47         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  48         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  49 #endif
  50         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  51         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  52         .tx_bd_ring_len         = 16,
  53         .rx_bd_ring_len         = 16,
  54         .phy_address            = CFG_UEC1_PHY_ADDR,
  55         .enet_interface         = CFG_UEC1_INTERFACE_MODE,
  56 };
  57 #endif
  58 #ifdef CONFIG_UEC_ETH2
  59 static uec_info_t eth2_uec_info = {
  60         .uf_info                = {
  61                 .ucc_num        = CFG_UEC2_UCC_NUM,
  62                 .rx_clock       = CFG_UEC2_RX_CLK,
  63                 .tx_clock       = CFG_UEC2_TX_CLK,
  64                 .eth_type       = CFG_UEC2_ETH_TYPE,
  65         },
  66 #if (CFG_UEC2_ETH_TYPE == FAST_ETH)
  67         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  68         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  69 #else
  70         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  71         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  72 #endif
  73         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  74         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  75         .tx_bd_ring_len         = 16,
  76         .rx_bd_ring_len         = 16,
  77         .phy_address            = CFG_UEC2_PHY_ADDR,
  78         .enet_interface         = CFG_UEC2_INTERFACE_MODE,
  79 };
  80 #endif
  81 #ifdef CONFIG_UEC_ETH3
  82 static uec_info_t eth3_uec_info = {
  83         .uf_info                = {
  84                 .ucc_num        = CFG_UEC3_UCC_NUM,
  85                 .rx_clock       = CFG_UEC3_RX_CLK,
  86                 .tx_clock       = CFG_UEC3_TX_CLK,
  87                 .eth_type       = CFG_UEC3_ETH_TYPE,
  88         },
  89 #if (CFG_UEC3_ETH_TYPE == FAST_ETH)
  90         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  91         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  92 #else
  93         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  94         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  95 #endif
  96         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  97         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  98         .tx_bd_ring_len         = 16,
  99         .rx_bd_ring_len         = 16,
 100         .phy_address            = CFG_UEC3_PHY_ADDR,
 101         .enet_interface         = CFG_UEC3_INTERFACE_MODE,
 102 };
 103 #endif
 104 #ifdef CONFIG_UEC_ETH4
 105 static uec_info_t eth4_uec_info = {
 106         .uf_info                = {
 107                 .ucc_num        = CFG_UEC4_UCC_NUM,
 108                 .rx_clock       = CFG_UEC4_RX_CLK,
 109                 .tx_clock       = CFG_UEC4_TX_CLK,
 110                 .eth_type       = CFG_UEC4_ETH_TYPE,
 111         },
 112 #if (CFG_UEC4_ETH_TYPE == FAST_ETH)
 113         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 114         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 115 #else
 116         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 117         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 118 #endif
 119         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 120         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 121         .tx_bd_ring_len         = 16,
 122         .rx_bd_ring_len         = 16,
 123         .phy_address            = CFG_UEC4_PHY_ADDR,
 124         .enet_interface         = CFG_UEC4_INTERFACE_MODE,
 125 };
 126 #endif
 127
 128 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 129 {
 130         uec_t           *uec_regs;
 131         u32             maccfg1;
 132
 133         if (!uec) {
 134                 printf("%s: uec not initial\n", __FUNCTION__);
 135                 return -EINVAL;
 136         }
 137         uec_regs = uec->uec_regs;
 138
 139         maccfg1 = in_be32(&uec_regs->maccfg1);
 140
 141         if (mode & COMM_DIR_TX) {
 142                 maccfg1 |= MACCFG1_ENABLE_TX;
 143                 out_be32(&uec_regs->maccfg1, maccfg1);
 144                 uec->mac_tx_enabled = 1;
 145         }
 146
 147         if (mode & COMM_DIR_RX) {
 148                 maccfg1 |= MACCFG1_ENABLE_RX;
 149                 out_be32(&uec_regs->maccfg1, maccfg1);
 150                 uec->mac_rx_enabled = 1;
 151         }
 152
 153         return 0;
 154 }
 155
 156 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
 157 {
 158         uec_t           *uec_regs;
 159         u32             maccfg1;
 160
 161         if (!uec) {
 162                 printf("%s: uec not initial\n", __FUNCTION__);
 163                 return -EINVAL;
 164         }
 165         uec_regs = uec->uec_regs;
 166
 167         maccfg1 = in_be32(&uec_regs->maccfg1);
 168
 169         if (mode & COMM_DIR_TX) {
 170                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 171                 out_be32(&uec_regs->maccfg1, maccfg1);
 172                 uec->mac_tx_enabled = 0;
 173         }
 174
 175         if (mode & COMM_DIR_RX) {
 176                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 177                 out_be32(&uec_regs->maccfg1, maccfg1);
 178                 uec->mac_rx_enabled = 0;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int uec_graceful_stop_tx(uec_private_t *uec)
 185 {
 186         ucc_fast_t              *uf_regs;
 187         u32                     cecr_subblock;
 188         u32                     ucce;
 189
 190         if (!uec || !uec->uccf) {
 191                 printf("%s: No handle passed.\n", __FUNCTION__);
 192                 return -EINVAL;
 193         }
 194
 195         uf_regs = uec->uccf->uf_regs;
 196
 197         /* Clear the grace stop event */
 198         out_be32(&uf_regs->ucce, UCCE_GRA);
 199
 200         /* Issue host command */
 201         cecr_subblock =
 202                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 203         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 204                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 205
 206         /* Wait for command to complete */
 207         do {
 208                 ucce = in_be32(&uf_regs->ucce);
 209         } while (! (ucce & UCCE_GRA));
 210
 211         uec->grace_stopped_tx = 1;
 212
 213         return 0;
 214 }
 215
 216 static int uec_graceful_stop_rx(uec_private_t *uec)
 217 {
 218         u32             cecr_subblock;
 219         u8              ack;
 220
 221         if (!uec) {
 222                 printf("%s: No handle passed.\n", __FUNCTION__);
 223                 return -EINVAL;
 224         }
 225
 226         if (!uec->p_rx_glbl_pram) {
 227                 printf("%s: No init rx global parameter\n", __FUNCTION__);
 228                 return -EINVAL;
 229         }
 230
 231         /* Clear acknowledge bit */
 232         ack = uec->p_rx_glbl_pram->rxgstpack;
 233         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 234         uec->p_rx_glbl_pram->rxgstpack = ack;
 235
 236         /* Keep issuing cmd and checking ack bit until it is asserted */
 237         do {
 238                 /* Issue host command */
 239                 cecr_subblock =
 240                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 241                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 242                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 243                 ack = uec->p_rx_glbl_pram->rxgstpack;
 244         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
 245
 246         uec->grace_stopped_rx = 1;
 247
 248         return 0;
 249 }
 250
 251 static int uec_restart_tx(uec_private_t *uec)
 252 {
 253         u32             cecr_subblock;
 254
 255         if (!uec || !uec->uec_info) {
 256                 printf("%s: No handle passed.\n", __FUNCTION__);
 257                 return -EINVAL;
 258         }
 259
 260         cecr_subblock =
 261          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 262         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 263                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 264
 265         uec->grace_stopped_tx = 0;
 266
 267         return 0;
 268 }
 269
 270 static int uec_restart_rx(uec_private_t *uec)
 271 {
 272         u32             cecr_subblock;
 273
 274         if (!uec || !uec->uec_info) {
 275                 printf("%s: No handle passed.\n", __FUNCTION__);
 276                 return -EINVAL;
 277         }
 278
 279         cecr_subblock =
 280          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 281         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 282                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 283
 284         uec->grace_stopped_rx = 0;
 285
 286         return 0;
 287 }
 288
 289 static int uec_open(uec_private_t *uec, comm_dir_e mode)
 290 {
 291         ucc_fast_private_t      *uccf;
 292
 293         if (!uec || !uec->uccf) {
 294                 printf("%s: No handle passed.\n", __FUNCTION__);
 295                 return -EINVAL;
 296         }
 297         uccf = uec->uccf;
 298
 299         /* check if the UCC number is in range. */
 300         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 301                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 302                 return -EINVAL;
 303         }
 304
 305         /* Enable MAC */
 306         uec_mac_enable(uec, mode);
 307
 308         /* Enable UCC fast */
 309         ucc_fast_enable(uccf, mode);
 310
 311         /* RISC microcode start */
 312         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
 313                 uec_restart_tx(uec);
 314         }
 315         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
 316                 uec_restart_rx(uec);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 323 {
 324         ucc_fast_private_t      *uccf;
 325
 326         if (!uec || !uec->uccf) {
 327                 printf("%s: No handle passed.\n", __FUNCTION__);
 328                 return -EINVAL;
 329         }
 330         uccf = uec->uccf;
 331
 332         /* check if the UCC number is in range. */
 333         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 334                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 335                 return -EINVAL;
 336         }
 337         /* Stop any transmissions */
 338         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
 339                 uec_graceful_stop_tx(uec);
 340         }
 341         /* Stop any receptions */
 342         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
 343                 uec_graceful_stop_rx(uec);
 344         }
 345
 346         /* Disable the UCC fast */
 347         ucc_fast_disable(uec->uccf, mode);
 348
 349         /* Disable the MAC */
 350         uec_mac_disable(uec, mode);
 351
 352         return 0;
 353 }
 354
 355 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 356 {
 357         uec_t           *uec_regs;
 358         u32             maccfg2;
 359
 360         if (!uec) {
 361                 printf("%s: uec not initial\n", __FUNCTION__);
 362                 return -EINVAL;
 363         }
 364         uec_regs = uec->uec_regs;
 365
 366         if (duplex == DUPLEX_HALF) {
 367                 maccfg2 = in_be32(&uec_regs->maccfg2);
 368                 maccfg2 &= ~MACCFG2_FDX;
 369                 out_be32(&uec_regs->maccfg2, maccfg2);
 370         }
 371
 372         if (duplex == DUPLEX_FULL) {
 373                 maccfg2 = in_be32(&uec_regs->maccfg2);
 374                 maccfg2 |= MACCFG2_FDX;
 375                 out_be32(&uec_regs->maccfg2, maccfg2);
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 382 {
 383         enet_interface_e        enet_if_mode;
 384         uec_info_t              *uec_info;
 385         uec_t                   *uec_regs;
 386         u32                     upsmr;
 387         u32                     maccfg2;
 388
 389         if (!uec) {
 390                 printf("%s: uec not initial\n", __FUNCTION__);
 391                 return -EINVAL;
 392         }
 393
 394         uec_info = uec->uec_info;
 395         uec_regs = uec->uec_regs;
 396         enet_if_mode = if_mode;
 397
 398         maccfg2 = in_be32(&uec_regs->maccfg2);
 399         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 400
 401         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 402         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 403
 404         switch (enet_if_mode) {
 405                 case ENET_100_MII:
 406                 case ENET_10_MII:
 407                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 408                         break;
 409                 case ENET_1000_GMII:
 410                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 411                         break;
 412                 case ENET_1000_TBI:
 413                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 414                         upsmr |= UPSMR_TBIM;
 415                         break;
 416                 case ENET_1000_RTBI:
 417                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 418                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 419                         break;
 420                 case ENET_1000_RGMII:
 421                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 422                         upsmr |= UPSMR_RPM;
 423                         break;
 424                 case ENET_100_RGMII:
 425                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 426                         upsmr |= UPSMR_RPM;
 427                         break;
 428                 case ENET_10_RGMII:
 429                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 430                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 431                         break;
 432                 case ENET_100_RMII:
 433                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 434                         upsmr |= UPSMR_RMM;
 435                         break;
 436                 case ENET_10_RMII:
 437                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 438                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 439                         break;
 440                 default:
 441                         return -EINVAL;
 442                         break;
 443         }
 444         out_be32(&uec_regs->maccfg2, maccfg2);
 445         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 446
 447         return 0;
 448 }
 449
 450 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 451 {
 452         uint            timeout = 0x1000;
 453         u32             miimcfg = 0;
 454
 455         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 456         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 457         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 458
 459         /* Wait until the bus is free */
 460         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 461         if (timeout <= 0) {
 462                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
 463                 return -ETIMEDOUT;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static int init_phy(struct eth_device *dev)
 470 {
 471         uec_private_t           *uec;
 472         uec_mii_t               *umii_regs;
 473         struct uec_mii_info     *mii_info;
 474         struct phy_info         *curphy;
 475         int                     err;
 476
 477         uec = (uec_private_t *)dev->priv;
 478         umii_regs = uec->uec_mii_regs;
 479
 480         uec->oldlink = 0;
 481         uec->oldspeed = 0;
 482         uec->oldduplex = -1;
 483
 484         mii_info = malloc(sizeof(*mii_info));
 485         if (!mii_info) {
 486                 printf("%s: Could not allocate mii_info", dev->name);
 487                 return -ENOMEM;
 488         }
 489         memset(mii_info, 0, sizeof(*mii_info));
 490
 491         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 492                 mii_info->speed = SPEED_1000;
 493         } else {
 494                 mii_info->speed = SPEED_100;
 495         }
 496
 497         mii_info->duplex = DUPLEX_FULL;
 498         mii_info->pause = 0;
 499         mii_info->link = 1;
 500
 501         mii_info->advertising = (ADVERTISED_10baseT_Half |
 502                                 ADVERTISED_10baseT_Full |
 503                                 ADVERTISED_100baseT_Half |
 504                                 ADVERTISED_100baseT_Full |
 505                                 ADVERTISED_1000baseT_Full);
 506         mii_info->autoneg = 1;
 507         mii_info->mii_id = uec->uec_info->phy_address;
 508         mii_info->dev = dev;
 509
 510         mii_info->mdio_read = &uec_read_phy_reg;
 511         mii_info->mdio_write = &uec_write_phy_reg;
 512
 513         uec->mii_info = mii_info;
 514
 515         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
 516
 517         if (init_mii_management_configuration(umii_regs)) {
 518                 printf("%s: The MII Bus is stuck!", dev->name);
 519                 err = -1;
 520                 goto bus_fail;
 521         }
 522
 523         /* get info for this PHY */
 524         curphy = uec_get_phy_info(uec->mii_info);
 525         if (!curphy) {
 526                 printf("%s: No PHY found", dev->name);
 527                 err = -1;
 528                 goto no_phy;
 529         }
 530
 531         mii_info->phyinfo = curphy;
 532
 533         /* Run the commands which initialize the PHY */
 534         if (curphy->init) {
 535                 err = curphy->init(uec->mii_info);
 536                 if (err)
 537                         goto phy_init_fail;
 538         }
 539
 540         return 0;
 541
 542 phy_init_fail:
 543 no_phy:
 544 bus_fail:
 545         free(mii_info);
 546         return err;
 547 }
 548
 549 static void adjust_link(struct eth_device *dev)
 550 {
 551         uec_private_t           *uec = (uec_private_t *)dev->priv;
 552         uec_t                   *uec_regs;
 553         struct uec_mii_info     *mii_info = uec->mii_info;
 554
 555         extern void change_phy_interface_mode(struct eth_device *dev,
 556                                          enet_interface_e mode);
 557         uec_regs = uec->uec_regs;
 558
 559         if (mii_info->link) {
 560                 /* Now we make sure that we can be in full duplex mode.
 561                 * If not, we operate in half-duplex mode. */
 562                 if (mii_info->duplex != uec->oldduplex) {
 563                         if (!(mii_info->duplex)) {
 564                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 565                                 printf("%s: Half Duplex\n", dev->name);
 566                         } else {
 567                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 568                                 printf("%s: Full Duplex\n", dev->name);
 569                         }
 570                         uec->oldduplex = mii_info->duplex;
 571                 }
 572
 573                 if (mii_info->speed != uec->oldspeed) {
 574                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 575                                 switch (mii_info->speed) {
 576                                 case 1000:
 577                                         break;
 578                                 case 100:
 579                                         printf ("switching to rgmii 100\n");
 580                                         /* change phy to rgmii 100 */
 581                                         change_phy_interface_mode(dev,
 582                                                                 ENET_100_RGMII);
 583                                         /* change the MAC interface mode */
 584                                         uec_set_mac_if_mode(uec,ENET_100_RGMII);
 585                                         break;
 586                                 case 10:
 587                                         printf ("switching to rgmii 10\n");
 588                                         /* change phy to rgmii 10 */
 589                                         change_phy_interface_mode(dev,
 590                                                                 ENET_10_RGMII);
 591                                         /* change the MAC interface mode */
 592                                         uec_set_mac_if_mode(uec,ENET_10_RGMII);
 593                                         break;
 594                                 default:
 595                                         printf("%s: Ack,Speed(%d)is illegal\n",
 596                                                 dev->name, mii_info->speed);
 597                                         break;
 598                                 }
 599                         }
 600
 601                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 602                         uec->oldspeed = mii_info->speed;
 603                 }
 604
 605                 if (!uec->oldlink) {
 606                         printf("%s: Link is up\n", dev->name);
 607                         uec->oldlink = 1;
 608                 }
 609
 610         } else { /* if (mii_info->link) */
 611                 if (uec->oldlink) {
 612                         printf("%s: Link is down\n", dev->name);
 613                         uec->oldlink = 0;
 614                         uec->oldspeed = 0;
 615                         uec->oldduplex = -1;
 616                 }
 617         }
 618 }
 619
 620 static void phy_change(struct eth_device *dev)
 621 {
 622         uec_private_t   *uec = (uec_private_t *)dev->priv;
 623
 624         /* Update the link, speed, duplex */
 625         uec->mii_info->phyinfo->read_status(uec->mii_info);
 626
 627         /* Adjust the interface according to speed */
 628         adjust_link(dev);
 629 }
 630
 631 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
 632 {
 633         uec_t           *uec_regs;
 634         u32             mac_addr1;
 635         u32             mac_addr2;
 636
 637         if (!uec) {
 638                 printf("%s: uec not initial\n", __FUNCTION__);
 639                 return -EINVAL;
 640         }
 641
 642         uec_regs = uec->uec_regs;
 643
 644         /* if a station address of 0x12345678ABCD, perform a write to
 645         MACSTNADDR1 of 0xCDAB7856,
 646         MACSTNADDR2 of 0x34120000 */
 647
 648         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
 649                         (mac_addr[3] << 8)  | (mac_addr[2]);
 650         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 651
 652         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 653         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 654
 655         return 0;
 656 }
 657
 658 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
 659                                          int *threads_num_ret)
 660 {
 661         int     num_threads_numerica;
 662
 663         switch (threads_num) {
 664                 case UEC_NUM_OF_THREADS_1:
 665                         num_threads_numerica = 1;
 666                         break;
 667                 case UEC_NUM_OF_THREADS_2:
 668                         num_threads_numerica = 2;
 669                         break;
 670                 case UEC_NUM_OF_THREADS_4:
 671                         num_threads_numerica = 4;
 672                         break;
 673                 case UEC_NUM_OF_THREADS_6:
 674                         num_threads_numerica = 6;
 675                         break;
 676                 case UEC_NUM_OF_THREADS_8:
 677                         num_threads_numerica = 8;
 678                         break;
 679                 default:
 680                         printf("%s: Bad number of threads value.",
 681                                  __FUNCTION__);
 682                         return -EINVAL;
 683         }
 684
 685         *threads_num_ret = num_threads_numerica;
 686
 687         return 0;
 688 }
 689
 690 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
 691 {
 692         uec_info_t      *uec_info;
 693         u32             end_bd;
 694         u8              bmrx = 0;
 695         int             i;
 696
 697         uec_info = uec->uec_info;
 698
 699         /* Alloc global Tx parameter RAM page */
 700         uec->tx_glbl_pram_offset = qe_muram_alloc(
 701                                 sizeof(uec_tx_global_pram_t),
 702                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 703         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
 704                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 705
 706         /* Zero the global Tx prameter RAM */
 707         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
 708
 709         /* Init global Tx parameter RAM */
 710
 711         /* TEMODER, RMON statistics disable, one Tx queue */
 712         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 713
 714         /* SQPTR */
 715         uec->send_q_mem_reg_offset = qe_muram_alloc(
 716                                 sizeof(uec_send_queue_qd_t),
 717                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 718         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
 719                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 720         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 721
 722         /* Setup the table with TxBDs ring */
 723         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 724                                          * SIZEOFBD;
 725         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 726                                  (u32)(uec->p_tx_bd_ring));
 727         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 728                                                  end_bd);
 729
 730         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 731         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 732
 733         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 734         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 735
 736         /* TSTATE, global snooping, big endian, the CSB bus selected */
 737         bmrx = BMR_INIT_VALUE;
 738         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 739
 740         /* IPH_Offset */
 741         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
 742                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 743         }
 744
 745         /* VTAG table */
 746         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
 747                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 748         }
 749
 750         /* TQPTR */
 751         uec->thread_dat_tx_offset = qe_muram_alloc(
 752                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
 753                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
 754
 755         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
 756                                 qe_muram_addr(uec->thread_dat_tx_offset);
 757         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 758 }
 759
 760 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
 761 {
 762         u8      bmrx = 0;
 763         int     i;
 764         uec_82xx_address_filtering_pram_t       *p_af_pram;
 765
 766         /* Allocate global Rx parameter RAM page */
 767         uec->rx_glbl_pram_offset = qe_muram_alloc(
 768                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 769         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
 770                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 771
 772         /* Zero Global Rx parameter RAM */
 773         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
 774
 775         /* Init global Rx parameter RAM */
 776         /* REMODER, Extended feature mode disable, VLAN disable,
 777          LossLess flow control disable, Receive firmware statisic disable,
 778          Extended address parsing mode disable, One Rx queues,
 779          Dynamic maximum/minimum frame length disable, IP checksum check
 780          disable, IP address alignment disable
 781         */
 782         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 783
 784         /* RQPTR */
 785         uec->thread_dat_rx_offset = qe_muram_alloc(
 786                         num_threads_rx * sizeof(uec_thread_data_rx_t),
 787                          UEC_THREAD_DATA_ALIGNMENT);
 788         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
 789                                 qe_muram_addr(uec->thread_dat_rx_offset);
 790         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 791
 792         /* Type_or_Len */
 793         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 794
 795         /* RxRMON base pointer, we don't need it */
 796         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 797
 798         /* IntCoalescingPTR, we don't need it, no interrupt */
 799         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 800
 801         /* RSTATE, global snooping, big endian, the CSB bus selected */
 802         bmrx = BMR_INIT_VALUE;
 803         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 804
 805         /* MRBLR */
 806         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 807
 808         /* RBDQPTR */
 809         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
 810                                 sizeof(uec_rx_bd_queues_entry_t) + \
 811                                 sizeof(uec_rx_prefetched_bds_t),
 812                                  UEC_RX_BD_QUEUES_ALIGNMENT);
 813         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
 814                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 815
 816         /* Zero it */
 817         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
 818                                         sizeof(uec_rx_prefetched_bds_t));
 819         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 820         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 821                  (u32)uec->p_rx_bd_ring);
 822
 823         /* MFLR */
 824         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 825         /* MINFLR */
 826         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 827         /* MAXD1 */
 828         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 829         /* MAXD2 */
 830         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 831         /* ECAM_PTR */
 832         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 833         /* L2QT */
 834         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 835         /* L3QT */
 836         for (i = 0; i < 8; i++) {
 837                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 838         }
 839
 840         /* VLAN_TYPE */
 841         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 842         /* TCI */
 843         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 844
 845         /* Clear PQ2 style address filtering hash table */
 846         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
 847                         uec->p_rx_glbl_pram->addressfiltering;
 848
 849         p_af_pram->iaddr_h = 0;
 850         p_af_pram->iaddr_l = 0;
 851         p_af_pram->gaddr_h = 0;
 852         p_af_pram->gaddr_l = 0;
 853 }
 854
 855 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
 856                                          int thread_tx, int thread_rx)
 857 {
 858         uec_init_cmd_pram_t             *p_init_enet_param;
 859         u32                             init_enet_param_offset;
 860         uec_info_t                      *uec_info;
 861         int                             i;
 862         int                             snum;
 863         u32                             init_enet_offset;
 864         u32                             entry_val;
 865         u32                             command;
 866         u32                             cecr_subblock;
 867
 868         uec_info = uec->uec_info;
 869
 870         /* Allocate init enet command parameter */
 871         uec->init_enet_param_offset = qe_muram_alloc(
 872                                         sizeof(uec_init_cmd_pram_t), 4);
 873         init_enet_param_offset = uec->init_enet_param_offset;
 874         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
 875                                 qe_muram_addr(uec->init_enet_param_offset);
 876
 877         /* Zero init enet command struct */
 878         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
 879
 880         /* Init the command struct */
 881         p_init_enet_param = uec->p_init_enet_param;
 882         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
 883         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
 884         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
 885         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
 886         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
 887         p_init_enet_param->largestexternallookupkeysize = 0;
 888
 889         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
 890                                          << ENET_INIT_PARAM_RGF_SHIFT;
 891         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
 892                                          << ENET_INIT_PARAM_TGF_SHIFT;
 893
 894         /* Init Rx global parameter pointer */
 895         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
 896                                                  (u32)uec_info->riscRx;
 897
 898         /* Init Rx threads */
 899         for (i = 0; i < (thread_rx + 1); i++) {
 900                 if ((snum = qe_get_snum()) < 0) {
 901                         printf("%s can not get snum\n", __FUNCTION__);
 902                         return -ENOMEM;
 903                 }
 904
 905                 if (i==0) {
 906                         init_enet_offset = 0;
 907                 } else {
 908                         init_enet_offset = qe_muram_alloc(
 909                                         sizeof(uec_thread_rx_pram_t),
 910                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
 911                 }
 912
 913                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 914                                  init_enet_offset | (u32)uec_info->riscRx;
 915                 p_init_enet_param->rxthread[i] = entry_val;
 916         }
 917
 918         /* Init Tx global parameter pointer */
 919         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
 920                                          (u32)uec_info->riscTx;
 921
 922         /* Init Tx threads */
 923         for (i = 0; i < thread_tx; i++) {
 924                 if ((snum = qe_get_snum()) < 0) {
 925                         printf("%s can not get snum\n", __FUNCTION__);
 926                         return -ENOMEM;
 927                 }
 928
 929                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
 930                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
 931
 932                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 933                                  init_enet_offset | (u32)uec_info->riscTx;
 934                 p_init_enet_param->txthread[i] = entry_val;
 935         }
 936
 937         __asm__ __volatile__("sync");
 938
 939         /* Issue QE command */
 940         command = QE_INIT_TX_RX;
 941         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 942                                 uec->uec_info->uf_info.ucc_num);
 943         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
 944                                                  init_enet_param_offset);
 945
 946         return 0;
 947 }
 948
 949 static int uec_startup(uec_private_t *uec)
 950 {
 951         uec_info_t                      *uec_info;
 952         ucc_fast_info_t                 *uf_info;
 953         ucc_fast_private_t              *uccf;
 954         ucc_fast_t                      *uf_regs;
 955         uec_t                           *uec_regs;
 956         int                             num_threads_tx;
 957         int                             num_threads_rx;
 958         u32                             utbipar;
 959         enet_interface_e                enet_interface;
 960         u32                             length;
 961         u32                             align;
 962         qe_bd_t                         *bd;
 963         u8                              *buf;
 964         int                             i;
 965
 966         if (!uec || !uec->uec_info) {
 967                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
 968                 return -EINVAL;
 969         }
 970
 971         uec_info = uec->uec_info;
 972         uf_info = &(uec_info->uf_info);
 973
 974         /* Check if Rx BD ring len is illegal */
 975         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
 976                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
 977                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
 978                          __FUNCTION__);
 979                 return -EINVAL;
 980         }
 981
 982         /* Check if Tx BD ring len is illegal */
 983         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
 984                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
 985                          __FUNCTION__);
 986                 return -EINVAL;
 987         }
 988
 989         /* Check if MRBLR is illegal */
 990         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
 991                 printf("%s: max rx buffer length must be mutliple of 128.\n",
 992                          __FUNCTION__);
 993                 return -EINVAL;
 994         }
 995
 996         /* Both Rx and Tx are stopped */
 997         uec->grace_stopped_rx = 1;
 998         uec->grace_stopped_tx = 1;
 999
1000         /* Init UCC fast */
1001         if (ucc_fast_init(uf_info, &uccf)) {
1002                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1003                 return -ENOMEM;
1004         }
1005
1006         /* Save uccf */
1007         uec->uccf = uccf;
1008
1009         /* Convert the Tx threads number */
1010         if (uec_convert_threads_num(uec_info->num_threads_tx,
1011                                          &num_threads_tx)) {
1012                 return -EINVAL;
1013         }
1014
1015         /* Convert the Rx threads number */
1016         if (uec_convert_threads_num(uec_info->num_threads_rx,
1017                                          &num_threads_rx)) {
1018                 return -EINVAL;
1019         }
1020
1021         uf_regs = uccf->uf_regs;
1022
1023         /* UEC register is following UCC fast registers */
1024         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1025
1026         /* Save the UEC register pointer to UEC private struct */
1027         uec->uec_regs = uec_regs;
1028
1029         /* Init UPSMR, enable hardware statistics (UCC) */
1030         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1031
1032         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1033         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1034
1035         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1036         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1037
1038         /* Setup MAC interface mode */
1039         uec_set_mac_if_mode(uec, uec_info->enet_interface);
1040
1041         /* Setup MII management base */
1042 #ifndef CONFIG_eTSEC_MDIO_BUS
1043         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1044 #else
1045         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1046 #endif
1047
1048         /* Setup MII master clock source */
1049         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1050
1051         /* Setup UTBIPAR */
1052         utbipar = in_be32(&uec_regs->utbipar);
1053         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1054         enet_interface = uec->uec_info->enet_interface;
1055         if (enet_interface == ENET_1000_TBI ||
1056                  enet_interface == ENET_1000_RTBI) {
1057                 utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
1058                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1059         } else {
1060                 utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
1061                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1062         }
1063
1064         out_be32(&uec_regs->utbipar, utbipar);
1065
1066         /* Allocate Tx BDs */
1067         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1068                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1069                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1070         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1071                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1072                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1073         }
1074
1075         align = UEC_TX_BD_RING_ALIGNMENT;
1076         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1077         if (uec->tx_bd_ring_offset != 0) {
1078                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1079                                                  & ~(align - 1));
1080         }
1081
1082         /* Zero all of Tx BDs */
1083         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1084
1085         /* Allocate Rx BDs */
1086         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1087         align = UEC_RX_BD_RING_ALIGNMENT;
1088         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1089         if (uec->rx_bd_ring_offset != 0) {
1090                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1091                                                          & ~(align - 1));
1092         }
1093
1094         /* Zero all of Rx BDs */
1095         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1096
1097         /* Allocate Rx buffer */
1098         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1099         align = UEC_RX_DATA_BUF_ALIGNMENT;
1100         uec->rx_buf_offset = (u32)malloc(length + align);
1101         if (uec->rx_buf_offset != 0) {
1102                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1103                                                  & ~(align - 1));
1104         }
1105
1106         /* Zero all of the Rx buffer */
1107         memset((void *)(uec->rx_buf_offset), 0, length + align);
1108
1109         /* Init TxBD ring */
1110         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1111         uec->txBd = bd;
1112
1113         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1114                 BD_DATA_CLEAR(bd);
1115                 BD_STATUS_SET(bd, 0);
1116                 BD_LENGTH_SET(bd, 0);
1117                 bd ++;
1118         }
1119         BD_STATUS_SET((--bd), TxBD_WRAP);
1120
1121         /* Init RxBD ring */
1122         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1123         uec->rxBd = bd;
1124         buf = uec->p_rx_buf;
1125         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1126                 BD_DATA_SET(bd, buf);
1127                 BD_LENGTH_SET(bd, 0);
1128                 BD_STATUS_SET(bd, RxBD_EMPTY);
1129                 buf += MAX_RXBUF_LEN;
1130                 bd ++;
1131         }
1132         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1133
1134         /* Init global Tx parameter RAM */
1135         uec_init_tx_parameter(uec, num_threads_tx);
1136
1137         /* Init global Rx parameter RAM */
1138         uec_init_rx_parameter(uec, num_threads_rx);
1139
1140         /* Init ethernet Tx and Rx parameter command */
1141         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1142                                          num_threads_rx)) {
1143                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1144                 return -ENOMEM;
1145         }
1146
1147         return 0;
1148 }
1149
1150 static int uec_init(struct eth_device* dev, bd_t *bd)
1151 {
1152         uec_private_t           *uec;
1153         int                     err, i;
1154         struct phy_info         *curphy;
1155
1156         uec = (uec_private_t *)dev->priv;
1157
1158         if (uec->the_first_run == 0) {
1159                 err = init_phy(dev);
1160                 if (err) {
1161                         printf("%s: Cannot initialize PHY, aborting.\n",
1162                                dev->name);
1163                         return err;
1164                 }
1165
1166                 curphy = uec->mii_info->phyinfo;
1167
1168                 if (curphy->config_aneg) {
1169                         err = curphy->config_aneg(uec->mii_info);
1170                         if (err) {
1171                                 printf("%s: Can't negotiate PHY\n", dev->name);
1172                                 return err;
1173                         }
1174                 }
1175
1176                 /* Give PHYs up to 5 sec to report a link */
1177                 i = 50;
1178                 do {
1179                         err = curphy->read_status(uec->mii_info);
1180                         udelay(100000);
1181                 } while (((i-- > 0) && !uec->mii_info->link) || err);
1182
1183                 if (err || i <= 0)
1184                         printf("warning: %s: timeout on PHY link\n", dev->name);
1185
1186                 uec->the_first_run = 1;
1187         }
1188
1189         /* Set up the MAC address */
1190         if (dev->enetaddr[0] & 0x01) {
1191                 printf("%s: MacAddress is multcast address\n",
1192                          __FUNCTION__);
1193                 return -1;
1194         }
1195         uec_set_mac_address(uec, dev->enetaddr);
1196
1197
1198         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1199         if (err) {
1200                 printf("%s: cannot enable UEC device\n", dev->name);
1201                 return -1;
1202         }
1203
1204         phy_change(dev);
1205
1206         return (uec->mii_info->link ? 0 : -1);
1207 }
1208
1209 static void uec_halt(struct eth_device* dev)
1210 {
1211         uec_private_t   *uec = (uec_private_t *)dev->priv;
1212         uec_stop(uec, COMM_DIR_RX_AND_TX);
1213 }
1214
1215 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1216 {
1217         uec_private_t           *uec;
1218         ucc_fast_private_t      *uccf;
1219         volatile qe_bd_t        *bd;
1220         u16                     status;
1221         int                     i;
1222         int                     result = 0;
1223
1224         uec = (uec_private_t *)dev->priv;
1225         uccf = uec->uccf;
1226         bd = uec->txBd;
1227
1228         /* Find an empty TxBD */
1229         for (i = 0; bd->status & TxBD_READY; i++) {
1230                 if (i > 0x100000) {
1231                         printf("%s: tx buffer not ready\n", dev->name);
1232                         return result;
1233                 }
1234         }
1235
1236         /* Init TxBD */
1237         BD_DATA_SET(bd, buf);
1238         BD_LENGTH_SET(bd, len);
1239         status = bd->status;
1240         status &= BD_WRAP;
1241         status |= (TxBD_READY | TxBD_LAST);
1242         BD_STATUS_SET(bd, status);
1243
1244         /* Tell UCC to transmit the buffer */
1245         ucc_fast_transmit_on_demand(uccf);
1246
1247         /* Wait for buffer to be transmitted */
1248         for (i = 0; bd->status & TxBD_READY; i++) {
1249                 if (i > 0x100000) {
1250                         printf("%s: tx error\n", dev->name);
1251                         return result;
1252                 }
1253         }
1254
1255         /* Ok, the buffer be transimitted */
1256         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1257         uec->txBd = bd;
1258         result = 1;
1259
1260         return result;
1261 }
1262
1263 static int uec_recv(struct eth_device* dev)
1264 {
1265         uec_private_t           *uec = dev->priv;
1266         volatile qe_bd_t        *bd;
1267         u16                     status;
1268         u16                     len;
1269         u8                      *data;
1270
1271         bd = uec->rxBd;
1272         status = bd->status;
1273
1274         while (!(status & RxBD_EMPTY)) {
1275                 if (!(status & RxBD_ERROR)) {
1276                         data = BD_DATA(bd);
1277                         len = BD_LENGTH(bd);
1278                         NetReceive(data, len);
1279                 } else {
1280                         printf("%s: Rx error\n", dev->name);
1281                 }
1282                 status &= BD_CLEAN;
1283                 BD_LENGTH_SET(bd, 0);
1284                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1285                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1286                 status = bd->status;
1287         }
1288         uec->rxBd = bd;
1289
1290         return 1;
1291 }
1292
1293 int uec_initialize(int index)
1294 {
1295         struct eth_device       *dev;
1296         int                     i;
1297         uec_private_t           *uec;
1298         uec_info_t              *uec_info;
1299         int                     err;
1300
1301         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1302         if (!dev)
1303                 return 0;
1304         memset(dev, 0, sizeof(struct eth_device));
1305
1306         /* Allocate the UEC private struct */
1307         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1308         if (!uec) {
1309                 return -ENOMEM;
1310         }
1311         memset(uec, 0, sizeof(uec_private_t));
1312
1313         /* Init UEC private struct, they come from board.h */
1314         uec_info = NULL;
1315         if (index == 0) {
1316 #ifdef CONFIG_UEC_ETH1
1317                 uec_info = &eth1_uec_info;
1318 #endif
1319         } else if (index == 1) {
1320 #ifdef CONFIG_UEC_ETH2
1321                 uec_info = &eth2_uec_info;
1322 #endif
1323         } else if (index == 2) {
1324 #ifdef CONFIG_UEC_ETH3
1325                 uec_info = &eth3_uec_info;
1326 #endif
1327         } else if (index == 3) {
1328 #ifdef CONFIG_UEC_ETH4
1329                 uec_info = &eth4_uec_info;
1330 #endif
1331         } else {
1332                 printf("%s: index is illegal.\n", __FUNCTION__);
1333                 return -EINVAL;
1334         }
1335
1336         uec->uec_info = uec_info;
1337
1338         sprintf(dev->name, "FSL UEC%d", index);
1339         dev->iobase = 0;
1340         dev->priv = (void *)uec;
1341         dev->init = uec_init;
1342         dev->halt = uec_halt;
1343         dev->send = uec_send;
1344         dev->recv = uec_recv;
1345
1346         /* Clear the ethnet address */
1347         for (i = 0; i < 6; i++)
1348                 dev->enetaddr[i] = 0;
1349
1350         eth_register(dev);
1351
1352         err = uec_startup(uec);
1353         if (err) {
1354                 printf("%s: Cannot configure net device, aborting.",dev->name);
1355                 return err;
1356         }
1357
1358         return 1;
1359 }
1360 #endif /* CONFIG_QE */