git.sur5r.net Git - u-boot/blob - drivers/qe/uec.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on source code of Shlomi Gridish
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __UEC_H__
  24 #define __UEC_H__
  25
  26 #define MAX_TX_THREADS                          8
  27 #define MAX_RX_THREADS                          8
  28 #define MAX_TX_QUEUES                           8
  29 #define MAX_RX_QUEUES                           8
  30 #define MAX_PREFETCHED_BDS                      4
  31 #define MAX_IPH_OFFSET_ENTRY                    8
  32 #define MAX_ENET_INIT_PARAM_ENTRIES_RX          9
  33 #define MAX_ENET_INIT_PARAM_ENTRIES_TX          8
  34
  35 /* UEC UPSMR (Protocol Specific Mode Register)
  36  */
  37 #define UPSMR_ECM       0x04000000 /* Enable CAM Miss               */
  38 #define UPSMR_HSE       0x02000000 /* Hardware Statistics Enable    */
  39 #define UPSMR_PRO       0x00400000 /* Promiscuous                   */
  40 #define UPSMR_CAP       0x00200000 /* CAM polarity                  */
  41 #define UPSMR_RSH       0x00100000 /* Receive Short Frames          */
  42 #define UPSMR_RPM       0x00080000 /* Reduced Pin Mode interfaces   */
  43 #define UPSMR_R10M      0x00040000 /* RGMII/RMII 10 Mode            */
  44 #define UPSMR_RLPB      0x00020000 /* RMII Loopback Mode            */
  45 #define UPSMR_TBIM      0x00010000 /* Ten-bit Interface Mode        */
  46 #define UPSMR_RMM       0x00001000 /* RMII/RGMII Mode               */
  47 #define UPSMR_CAM       0x00000400 /* CAM Address Matching          */
  48 #define UPSMR_BRO       0x00000200 /* Broadcast Address             */
  49 #define UPSMR_RES1      0x00002000 /* Reserved feild - must be 1    */
  50
  51 #define UPSMR_INIT_VALUE        (UPSMR_HSE | UPSMR_RES1)
  52
  53 /* UEC MACCFG1 (MAC Configuration 1 Register)
  54  */
  55 #define MACCFG1_FLOW_RX                 0x00000020 /* Flow Control Rx */
  56 #define MACCFG1_FLOW_TX                 0x00000010 /* Flow Control Tx */
  57 #define MACCFG1_ENABLE_SYNCHED_RX       0x00000008 /* Enable Rx Sync  */
  58 #define MACCFG1_ENABLE_RX               0x00000004 /* Enable Rx       */
  59 #define MACCFG1_ENABLE_SYNCHED_TX       0x00000002 /* Enable Tx Sync  */
  60 #define MACCFG1_ENABLE_TX               0x00000001 /* Enable Tx       */
  61
  62 #define MACCFG1_INIT_VALUE              (0)
  63
  64 /* UEC MACCFG2 (MAC Configuration 2 Register)
  65  */
  66 #define MACCFG2_PREL                            0x00007000
  67 #define MACCFG2_PREL_SHIFT                      (31 - 19)
  68 #define MACCFG2_PREL_MASK                       0x0000f000
  69 #define MACCFG2_SRP                             0x00000080
  70 #define MACCFG2_STP                             0x00000040
  71 #define MACCFG2_RESERVED_1                      0x00000020 /* must be set  */
  72 #define MACCFG2_LC                              0x00000010 /* Length Check */
  73 #define MACCFG2_MPE                             0x00000008
  74 #define MACCFG2_FDX                             0x00000001 /* Full Duplex  */
  75 #define MACCFG2_FDX_MASK                        0x00000001
  76 #define MACCFG2_PAD_CRC                         0x00000004
  77 #define MACCFG2_CRC_EN                          0x00000002
  78 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000
  79 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002
  80 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
  81 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100
  82 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200
  83 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300
  84
  85 #define MACCFG2_INIT_VALUE      (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
  86                                  MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
  87
  88 /* UEC Event Register
  89 */
  90 #define UCCE_MPD                                0x80000000
  91 #define UCCE_SCAR                               0x40000000
  92 #define UCCE_GRA                                0x20000000
  93 #define UCCE_CBPR                               0x10000000
  94 #define UCCE_BSY                                0x08000000
  95 #define UCCE_RXC                                0x04000000
  96 #define UCCE_TXC                                0x02000000
  97 #define UCCE_TXE                                0x01000000
  98 #define UCCE_TXB7                               0x00800000
  99 #define UCCE_TXB6                               0x00400000
 100 #define UCCE_TXB5                               0x00200000
 101 #define UCCE_TXB4                               0x00100000
 102 #define UCCE_TXB3                               0x00080000
 103 #define UCCE_TXB2                               0x00040000
 104 #define UCCE_TXB1                               0x00020000
 105 #define UCCE_TXB0                               0x00010000
 106 #define UCCE_RXB7                               0x00008000
 107 #define UCCE_RXB6                               0x00004000
 108 #define UCCE_RXB5                               0x00002000
 109 #define UCCE_RXB4                               0x00001000
 110 #define UCCE_RXB3                               0x00000800
 111 #define UCCE_RXB2                               0x00000400
 112 #define UCCE_RXB1                               0x00000200
 113 #define UCCE_RXB0                               0x00000100
 114 #define UCCE_RXF7                               0x00000080
 115 #define UCCE_RXF6                               0x00000040
 116 #define UCCE_RXF5                               0x00000020
 117 #define UCCE_RXF4                               0x00000010
 118 #define UCCE_RXF3                               0x00000008
 119 #define UCCE_RXF2                               0x00000004
 120 #define UCCE_RXF1                               0x00000002
 121 #define UCCE_RXF0                               0x00000001
 122
 123 #define UCCE_TXB        (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
 124                          UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
 125 #define UCCE_RXB        (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
 126                          UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
 127 #define UCCE_RXF        (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
 128                          UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
 129 #define UCCE_OTHER      (UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
 130                          UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
 131
 132 /* UEC TEMODR Register
 133 */
 134 #define TEMODER_SCHEDULER_ENABLE                0x2000
 135 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400
 136 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200
 137 #define TEMODER_RMON_STATISTICS                 0x0100
 138 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15)
 139
 140 #define TEMODER_INIT_VALUE                      0xc000
 141
 142 /* UEC REMODR Register
 143 */
 144 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000
 145 #define REMODER_RX_EXTENDED_FEATURES            0x80000000
 146 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 )
 147 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
 148 #define REMODER_RX_QOS_MODE_SHIFT               (31-15)
 149 #define REMODER_RMON_STATISTICS                 0x00001000
 150 #define REMODER_RX_EXTENDED_FILTERING           0x00000800
 151 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23)
 152 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008
 153 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004
 154 #define REMODER_IP_CHECKSUM_CHECK               0x00000002
 155 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001
 156
 157 #define REMODER_INIT_VALUE                      0
 158
 159 /* BMRx - Bus Mode Register */
 160 #define BMR_GLB                                 0x20
 161 #define BMR_BO_BE                               0x10
 162 #define BMR_DTB_SECONDARY_BUS                   0x02
 163 #define BMR_BDB_SECONDARY_BUS                   0x01
 164
 165 #define BMR_SHIFT                               24
 166 #define BMR_INIT_VALUE                          (BMR_GLB | BMR_BO_BE)
 167
 168 /* UEC UCCS (Ethernet Status Register)
 169  */
 170 #define UCCS_BPR                                0x02
 171 #define UCCS_PAU                                0x02
 172 #define UCCS_MPD                                0x01
 173
 174 /* UEC MIIMCFG (MII Management Configuration Register)
 175  */
 176 #define MIIMCFG_RESET_MANAGEMENT                0x80000000
 177 #define MIIMCFG_NO_PREAMBLE                     0x00000010
 178 #define MIIMCFG_CLOCK_DIVIDE_SHIFT              (31 - 31)
 179 #define MIIMCFG_CLOCK_DIVIDE_MASK               0x0000000f
 180 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4    0x00000001
 181 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6    0x00000002
 182 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8    0x00000003
 183 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10   0x00000004
 184 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14   0x00000005
 185 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20   0x00000006
 186 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28   0x00000007
 187
 188 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE       \
 189         MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
 190
 191 /* UEC MIIMCOM (MII Management Command Register)
 192  */
 193 #define MIIMCOM_SCAN_CYCLE                      0x00000002 /* Scan cycle */
 194 #define MIIMCOM_READ_CYCLE                      0x00000001 /* Read cycle */
 195
 196 /* UEC MIIMADD (MII Management Address Register)
 197  */
 198 #define MIIMADD_PHY_ADDRESS_SHIFT               (31 - 23)
 199 #define MIIMADD_PHY_REGISTER_SHIFT              (31 - 31)
 200
 201 /* UEC MIIMCON (MII Management Control Register)
 202  */
 203 #define MIIMCON_PHY_CONTROL_SHIFT               (31 - 31)
 204 #define MIIMCON_PHY_STATUS_SHIFT                (31 - 31)
 205
 206 /* UEC MIIMIND (MII Management Indicator Register)
 207  */
 208 #define MIIMIND_NOT_VALID                       0x00000004
 209 #define MIIMIND_SCAN                            0x00000002
 210 #define MIIMIND_BUSY                            0x00000001
 211
 212 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
 213  */
 214 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)
 215 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f
 216
 217 /* UEC UESCR (Ethernet Statistics Control Register)
 218  */
 219 #define UESCR_AUTOZ                             0x8000
 220 #define UESCR_CLRCNT                            0x4000
 221 #define UESCR_MAXCOV_SHIFT                      (15 -  7)
 222 #define UESCR_SCOV_SHIFT                        (15 - 15)
 223
 224 /****** Tx data struct collection ******/
 225 /* Tx thread data, each Tx thread has one this struct.
 226 */
 227 typedef struct uec_thread_data_tx {
 228         u8   res0[136];
 229 } __attribute__ ((packed)) uec_thread_data_tx_t;
 230
 231 /* Tx thread parameter, each Tx thread has one this struct.
 232 */
 233 typedef struct uec_thread_tx_pram {
 234         u8   res0[64];
 235 } __attribute__ ((packed)) uec_thread_tx_pram_t;
 236
 237 /* Send queue queue-descriptor, each Tx queue has one this QD
 238 */
 239 typedef struct uec_send_queue_qd {
 240         u32    bd_ring_base; /* pointer to BD ring base address */
 241         u8     res0[0x8];
 242         u32    last_bd_completed_address; /* last entry in BD ring */
 243         u8     res1[0x30];
 244 } __attribute__ ((packed)) uec_send_queue_qd_t;
 245
 246 /* Send queue memory region */
 247 typedef struct uec_send_queue_mem_region {
 248         uec_send_queue_qd_t   sqqd[MAX_TX_QUEUES];
 249 } __attribute__ ((packed)) uec_send_queue_mem_region_t;
 250
 251 /* Scheduler struct
 252 */
 253 typedef struct uec_scheduler {
 254         u16  cpucount0;        /* CPU packet counter */
 255         u16  cpucount1;        /* CPU packet counter */
 256         u16  cecount0;         /* QE  packet counter */
 257         u16  cecount1;         /* QE  packet counter */
 258         u16  cpucount2;        /* CPU packet counter */
 259         u16  cpucount3;        /* CPU packet counter */
 260         u16  cecount2;         /* QE  packet counter */
 261         u16  cecount3;         /* QE  packet counter */
 262         u16  cpucount4;        /* CPU packet counter */
 263         u16  cpucount5;        /* CPU packet counter */
 264         u16  cecount4;         /* QE  packet counter */
 265         u16  cecount5;         /* QE  packet counter */
 266         u16  cpucount6;        /* CPU packet counter */
 267         u16  cpucount7;        /* CPU packet counter */
 268         u16  cecount6;         /* QE  packet counter */
 269         u16  cecount7;         /* QE  packet counter */
 270         u32  weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
 271         u32  rtsrshadow;       /* temporary variable handled by QE */
 272         u32  time;             /* temporary variable handled by QE */
 273         u32  ttl;              /* temporary variable handled by QE */
 274         u32  mblinterval;      /* max burst length interval        */
 275         u16  nortsrbytetime;   /* normalized value of byte time in tsr units */
 276         u8   fracsiz;
 277         u8   res0[1];
 278         u8   strictpriorityq;  /* Strict Priority Mask register */
 279         u8   txasap;           /* Transmit ASAP register        */
 280         u8   extrabw;          /* Extra BandWidth register      */
 281         u8   oldwfqmask;       /* temporary variable handled by QE */
 282         u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
 283         u32  minw;             /* temporary variable handled by QE */
 284         u8   res1[0x70-0x64];
 285 } __attribute__ ((packed)) uec_scheduler_t;
 286
 287 /* Tx firmware counters
 288 */
 289 typedef struct uec_tx_firmware_statistics_pram {
 290         u32  sicoltx;            /* single collision */
 291         u32  mulcoltx;           /* multiple collision */
 292         u32  latecoltxfr;        /* late collision */
 293         u32  frabortduecol;      /* frames aborted due to tx collision */
 294         u32  frlostinmactxer;    /* frames lost due to internal MAC error tx */
 295         u32  carriersenseertx;   /* carrier sense error */
 296         u32  frtxok;             /* frames transmitted OK */
 297         u32  txfrexcessivedefer;
 298         u32  txpkts256;          /* total packets(including bad) 256~511 B */
 299         u32  txpkts512;          /* total packets(including bad) 512~1023B */
 300         u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
 301         u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
 302 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
 303
 304 /* Tx global parameter table
 305 */
 306 typedef struct uec_tx_global_pram {
 307         u16  temoder;
 308         u8   res0[0x38-0x02];
 309         u32  sqptr;
 310         u32  schedulerbasepointer;
 311         u32  txrmonbaseptr;
 312         u32  tstate;
 313         u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
 314         u32  vtagtable[0x8];
 315         u32  tqptr;
 316         u8   res2[0x80-0x74];
 317 } __attribute__ ((packed)) uec_tx_global_pram_t;
 318
 319
 320 /****** Rx data struct collection ******/
 321 /* Rx thread data, each Rx thread has one this struct.
 322 */
 323 typedef struct uec_thread_data_rx {
 324         u8   res0[40];
 325 } __attribute__ ((packed)) uec_thread_data_rx_t;
 326
 327 /* Rx thread parameter, each Rx thread has one this struct.
 328 */
 329 typedef struct uec_thread_rx_pram {
 330         u8   res0[128];
 331 } __attribute__ ((packed)) uec_thread_rx_pram_t;
 332
 333 /* Rx firmware counters
 334 */
 335 typedef struct uec_rx_firmware_statistics_pram {
 336         u32   frrxfcser;         /* frames with crc error */
 337         u32   fraligner;         /* frames with alignment error */
 338         u32   inrangelenrxer;    /* in range length error */
 339         u32   outrangelenrxer;   /* out of range length error */
 340         u32   frtoolong;         /* frame too long */
 341         u32   runt;              /* runt */
 342         u32   verylongevent;     /* very long event */
 343         u32   symbolerror;       /* symbol error */
 344         u32   dropbsy;           /* drop because of BD not ready */
 345         u8    res0[0x8];
 346         u32   mismatchdrop;      /* drop because of MAC filtering */
 347         u32   underpkts;         /* total frames less than 64 octets */
 348         u32   pkts256;           /* total frames(including bad)256~511 B */
 349         u32   pkts512;           /* total frames(including bad)512~1023 B */
 350         u32   pkts1024;          /* total frames(including bad)1024~1518 B */
 351         u32   pktsjumbo;         /* total frames(including bad) >1024 B */
 352         u32   frlossinmacer;
 353         u32   pausefr;           /* pause frames */
 354         u8    res1[0x4];
 355         u32   removevlan;
 356         u32   replacevlan;
 357         u32   insertvlan;
 358 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
 359
 360 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
 361 */
 362 typedef struct uec_rx_interrupt_coalescing_entry {
 363         u32   maxvalue;
 364         u32   counter;
 365 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
 366
 367 typedef struct uec_rx_interrupt_coalescing_table {
 368         uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
 369 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
 370
 371 /* RxBD queue entry, each Rx queue has one this entry.
 372 */
 373 typedef struct uec_rx_bd_queues_entry {
 374         u32   bdbaseptr;         /* BD base pointer          */
 375         u32   bdptr;             /* BD pointer               */
 376         u32   externalbdbaseptr; /* external BD base pointer */
 377         u32   externalbdptr;     /* external BD pointer      */
 378 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
 379
 380 /* Rx global paramter table
 381 */
 382 typedef struct uec_rx_global_pram {
 383         u32  remoder;             /* ethernet mode reg. */
 384         u32  rqptr;               /* base pointer to the Rx Queues */
 385         u32  res0[0x1];
 386         u8   res1[0x20-0xC];
 387         u16  typeorlen;
 388         u8   res2[0x1];
 389         u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
 390         u32  rxrmonbaseptr;       /* Rx RMON statistics base */
 391         u8   res3[0x30-0x28];
 392         u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
 393         u8   res4[0x36-0x34];
 394         u8   rstate;
 395         u8   res5[0x46-0x37];
 396         u16  mrblr;               /* max receive buffer length reg. */
 397         u32  rbdqptr;             /* RxBD parameter table description */
 398         u16  mflr;                /* max frame length reg. */
 399         u16  minflr;              /* min frame length reg. */
 400         u16  maxd1;               /* max dma1 length reg. */
 401         u16  maxd2;               /* max dma2 length reg. */
 402         u32  ecamptr;             /* external CAM address */
 403         u32  l2qt;                /* VLAN priority mapping table. */
 404         u32  l3qt[0x8];           /* IP   priority mapping table. */
 405         u16  vlantype;            /* vlan type */
 406         u16  vlantci;             /* default vlan tci */
 407         u8   addressfiltering[64];/* address filtering data structure */
 408         u32  exfGlobalParam;      /* extended filtering global parameters */
 409         u8   res6[0x100-0xC4];    /* Initialize to zero */
 410 } __attribute__ ((packed)) uec_rx_global_pram_t;
 411
 412 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 413
 414
 415 /****** UEC common ******/
 416 /* UCC statistics - hardware counters
 417 */
 418 typedef struct uec_hardware_statistics {
 419         u32 tx64;
 420         u32 tx127;
 421         u32 tx255;
 422         u32 rx64;
 423         u32 rx127;
 424         u32 rx255;
 425         u32 txok;
 426         u16 txcf;
 427         u32 tmca;
 428         u32 tbca;
 429         u32 rxfok;
 430         u32 rxbok;
 431         u32 rbyt;
 432         u32 rmca;
 433         u32 rbca;
 434 } __attribute__ ((packed)) uec_hardware_statistics_t;
 435
 436 /* InitEnet command parameter
 437 */
 438 typedef struct uec_init_cmd_pram {
 439         u8   resinit0;
 440         u8   resinit1;
 441         u8   resinit2;
 442         u8   resinit3;
 443         u16  resinit4;
 444         u8   res1[0x1];
 445         u8   largestexternallookupkeysize;
 446         u32  rgftgfrxglobal;
 447         u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
 448         u8   res2[0x38 - 0x30];
 449         u32  txglobal;                             /* tx global  */
 450         u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
 451         u8   res3[0x1];
 452 } __attribute__ ((packed)) uec_init_cmd_pram_t;
 453
 454 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 455 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 456
 457 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 458 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 459 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 460 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 461
 462 #define ENET_INIT_PARAM_MAGIC_RES_INIT0         0x06
 463 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x30
 464 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0xff
 465 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0x00
 466 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x0400
 467
 468 /* structure representing 82xx Address Filtering Enet Address in PRAM
 469 */
 470 typedef struct uec_82xx_enet_address {
 471         u8   res1[0x2];
 472         u16  h;       /* address (MSB) */
 473         u16  m;       /* address       */
 474         u16  l;       /* address (LSB) */
 475 } __attribute__ ((packed)) uec_82xx_enet_address_t;
 476
 477 /* structure representing 82xx Address Filtering PRAM
 478 */
 479 typedef struct uec_82xx_address_filtering_pram {
 480         u32  iaddr_h;        /* individual address filter, high */
 481         u32  iaddr_l;        /* individual address filter, low  */
 482         u32  gaddr_h;        /* group address filter, high      */
 483         u32  gaddr_l;        /* group address filter, low       */
 484         uec_82xx_enet_address_t    taddr;
 485         uec_82xx_enet_address_t    paddr[4];
 486         u8                         res0[0x40-0x38];
 487 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
 488
 489 /* Buffer Descriptor
 490 */
 491 typedef struct buffer_descriptor {
 492         u16 status;
 493         u16 len;
 494         u32 data;
 495 } __attribute__ ((packed)) qe_bd_t, *p_bd_t;
 496
 497 #define SIZEOFBD                sizeof(qe_bd_t)
 498
 499 /* Common BD flags
 500 */
 501 #define BD_WRAP                 0x2000
 502 #define BD_INT                  0x1000
 503 #define BD_LAST                 0x0800
 504 #define BD_CLEAN                0x3000
 505
 506 /* TxBD status flags
 507 */
 508 #define TxBD_READY              0x8000
 509 #define TxBD_PADCRC             0x4000
 510 #define TxBD_WRAP               BD_WRAP
 511 #define TxBD_INT                BD_INT
 512 #define TxBD_LAST               BD_LAST
 513 #define TxBD_TXCRC              0x0400
 514 #define TxBD_DEF                0x0200
 515 #define TxBD_PP                 0x0100
 516 #define TxBD_LC                 0x0080
 517 #define TxBD_RL                 0x0040
 518 #define TxBD_RC                 0x003C
 519 #define TxBD_UNDERRUN           0x0002
 520 #define TxBD_TRUNC              0x0001
 521
 522 #define TxBD_ERROR              (TxBD_UNDERRUN | TxBD_TRUNC)
 523
 524 /* RxBD status flags
 525 */
 526 #define RxBD_EMPTY              0x8000
 527 #define RxBD_OWNER              0x4000
 528 #define RxBD_WRAP               BD_WRAP
 529 #define RxBD_INT                BD_INT
 530 #define RxBD_LAST               BD_LAST
 531 #define RxBD_FIRST              0x0400
 532 #define RxBD_CMR                0x0200
 533 #define RxBD_MISS               0x0100
 534 #define RxBD_BCAST              0x0080
 535 #define RxBD_MCAST              0x0040
 536 #define RxBD_LG                 0x0020
 537 #define RxBD_NO                 0x0010
 538 #define RxBD_SHORT              0x0008
 539 #define RxBD_CRCERR             0x0004
 540 #define RxBD_OVERRUN            0x0002
 541 #define RxBD_IPCH               0x0001
 542
 543 #define RxBD_ERROR              (RxBD_LG | RxBD_NO | RxBD_SHORT | \
 544                                  RxBD_CRCERR | RxBD_OVERRUN)
 545
 546 /* BD access macros
 547 */
 548 #define BD_STATUS(_bd)                  (((p_bd_t)(_bd))->status)
 549 #define BD_STATUS_SET(_bd, _val)        (((p_bd_t)(_bd))->status = _val)
 550 #define BD_LENGTH(_bd)                  (((p_bd_t)(_bd))->len)
 551 #define BD_LENGTH_SET(_bd, _val)        (((p_bd_t)(_bd))->len = _val)
 552 #define BD_DATA_CLEAR(_bd)              (((p_bd_t)(_bd))->data = 0)
 553 #define BD_IS_DATA(_bd)                 (((p_bd_t)(_bd))->data)
 554 #define BD_DATA(_bd)                    ((u8 *)(((p_bd_t)(_bd))->data))
 555 #define BD_DATA_SET(_bd, _data)         (((p_bd_t)(_bd))->data = (u32)(_data))
 556 #define BD_ADVANCE(_bd,_status,_base)   \
 557         (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
 558
 559 /* Rx Prefetched BDs
 560 */
 561 typedef struct uec_rx_prefetched_bds {
 562     qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
 563 } __attribute__ ((packed)) uec_rx_prefetched_bds_t;
 564
 565 /* Alignments
 566  */
 567 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT                            64
 568 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT                            64
 569 #define UEC_THREAD_RX_PRAM_ALIGNMENT                            128
 570 #define UEC_THREAD_TX_PRAM_ALIGNMENT                            64
 571 #define UEC_THREAD_DATA_ALIGNMENT                               256
 572 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT               32
 573 #define UEC_SCHEDULER_ALIGNMENT                                 4
 574 #define UEC_TX_STATISTICS_ALIGNMENT                             4
 575 #define UEC_RX_STATISTICS_ALIGNMENT                             4
 576 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT                   4
 577 #define UEC_RX_BD_QUEUES_ALIGNMENT                              8
 578 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT                         128
 579 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT   4
 580 #define UEC_RX_BD_RING_ALIGNMENT                                32
 581 #define UEC_TX_BD_RING_ALIGNMENT                                32
 582 #define UEC_MRBLR_ALIGNMENT                                     128
 583 #define UEC_RX_BD_RING_SIZE_ALIGNMENT                           4
 584 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT                    32
 585 #define UEC_RX_DATA_BUF_ALIGNMENT                               64
 586
 587 #define UEC_VLAN_PRIORITY_MAX                                   8
 588 #define UEC_IP_PRIORITY_MAX                                     64
 589 #define UEC_TX_VTAG_TABLE_ENTRY_MAX                             8
 590 #define UEC_RX_BD_RING_SIZE_MIN                                 8
 591 #define UEC_TX_BD_RING_SIZE_MIN                                 2
 592
 593 /* Ethernet speed
 594 */
 595 typedef enum enet_speed {
 596         ENET_SPEED_10BT,   /* 10 Base T */
 597         ENET_SPEED_100BT,  /* 100 Base T */
 598         ENET_SPEED_1000BT  /* 1000 Base T */
 599 } enet_speed_e;
 600
 601 /* Ethernet Address Type.
 602 */
 603 typedef enum enet_addr_type {
 604         ENET_ADDR_TYPE_INDIVIDUAL,
 605         ENET_ADDR_TYPE_GROUP,
 606         ENET_ADDR_TYPE_BROADCAST
 607 } enet_addr_type_e;
 608
 609 /* TBI / MII Set Register
 610 */
 611 typedef enum enet_tbi_mii_reg {
 612         ENET_TBI_MII_CR        = 0x00,
 613         ENET_TBI_MII_SR        = 0x01,
 614         ENET_TBI_MII_ANA       = 0x04,
 615         ENET_TBI_MII_ANLPBPA   = 0x05,
 616         ENET_TBI_MII_ANEX      = 0x06,
 617         ENET_TBI_MII_ANNPT     = 0x07,
 618         ENET_TBI_MII_ANLPANP   = 0x08,
 619         ENET_TBI_MII_EXST      = 0x0F,
 620         ENET_TBI_MII_JD        = 0x10,
 621         ENET_TBI_MII_TBICON    = 0x11
 622 } enet_tbi_mii_reg_e;
 623
 624 /* UEC number of threads
 625 */
 626 typedef enum uec_num_of_threads {
 627         UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
 628         UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
 629         UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
 630         UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
 631         UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
 632 } uec_num_of_threads_e;
 633
 634 /* UEC ethernet interface type
 635 */
 636 typedef enum enet_interface {
 637         ENET_10_MII,
 638         ENET_10_RMII,
 639         ENET_10_RGMII,
 640         ENET_100_MII,
 641         ENET_100_RMII,
 642         ENET_100_RGMII,
 643         ENET_1000_GMII,
 644         ENET_1000_RGMII,
 645         ENET_1000_TBI,
 646         ENET_1000_RTBI
 647 } enet_interface_e;
 648
 649 /* UEC initialization info struct
 650 */
 651 typedef struct uec_info {
 652         ucc_fast_info_t                 uf_info;
 653         uec_num_of_threads_e            num_threads_tx;
 654         uec_num_of_threads_e            num_threads_rx;
 655         qe_risc_allocation_e            riscTx;
 656         qe_risc_allocation_e            riscRx;
 657         u16                             rx_bd_ring_len;
 658         u16                             tx_bd_ring_len;
 659         u8                              phy_address;
 660         enet_interface_e                enet_interface;
 661 } uec_info_t;
 662
 663 /* UEC driver initialized info
 664 */
 665 #define MAX_RXBUF_LEN                   1536
 666 #define MAX_FRAME_LEN                   1518
 667 #define MIN_FRAME_LEN                   64
 668 #define MAX_DMA1_LEN                    1520
 669 #define MAX_DMA2_LEN                    1520
 670
 671 /* UEC driver private struct
 672 */
 673 typedef struct uec_private {
 674         uec_info_t                      *uec_info;
 675         ucc_fast_private_t              *uccf;
 676         struct eth_device               *dev;
 677         uec_t                           *uec_regs;
 678         uec_mii_t                       *uec_mii_regs;
 679         /* enet init command parameter */
 680         uec_init_cmd_pram_t             *p_init_enet_param;
 681         u32                             init_enet_param_offset;
 682         /* Rx and Tx paramter */
 683         uec_rx_global_pram_t            *p_rx_glbl_pram;
 684         u32                             rx_glbl_pram_offset;
 685         uec_tx_global_pram_t            *p_tx_glbl_pram;
 686         u32                             tx_glbl_pram_offset;
 687         uec_send_queue_mem_region_t     *p_send_q_mem_reg;
 688         u32                             send_q_mem_reg_offset;
 689         uec_thread_data_tx_t            *p_thread_data_tx;
 690         u32                             thread_dat_tx_offset;
 691         uec_thread_data_rx_t            *p_thread_data_rx;
 692         u32                             thread_dat_rx_offset;
 693         uec_rx_bd_queues_entry_t        *p_rx_bd_qs_tbl;
 694         u32                             rx_bd_qs_tbl_offset;
 695         /* BDs specific */
 696         u8                              *p_tx_bd_ring;
 697         u32                             tx_bd_ring_offset;
 698         u8                              *p_rx_bd_ring;
 699         u32                             rx_bd_ring_offset;
 700         u8                              *p_rx_buf;
 701         u32                             rx_buf_offset;
 702         volatile qe_bd_t                *txBd;
 703         volatile qe_bd_t                *rxBd;
 704         /* Status */
 705         int                             mac_tx_enabled;
 706         int                             mac_rx_enabled;
 707         int                             grace_stopped_tx;
 708         int                             grace_stopped_rx;
 709         int                             the_first_run;
 710         /* PHY specific */
 711         struct uec_mii_info             *mii_info;
 712         int                             oldspeed;
 713         int                             oldduplex;
 714         int                             oldlink;
 715 } uec_private_t;
 716
 717 #endif /* __UEC_H__ */