2 * Copyright (c) 2017 Microchip Technology Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
12 /* LAN78xx specific register/bit defines */
13 #define LAN78XX_HW_CFG_LED1_EN BIT(21) /* Muxed with EEDO */
14 #define LAN78XX_HW_CFG_LED0_EN BIT(20) /* Muxed with EECLK */
16 #define LAN78XX_USB_CFG0 0x080
17 #define LAN78XX_USB_CFG0_BIR BIT(6)
19 #define LAN78XX_BURST_CAP 0x090
21 #define LAN78XX_BULK_IN_DLY 0x094
23 #define LAN78XX_RFE_CTL 0x0B0
25 #define LAN78XX_FCT_RX_CTL 0x0C0
27 #define LAN78XX_FCT_TX_CTL 0x0C4
29 #define LAN78XX_FCT_RX_FIFO_END 0x0C8
31 #define LAN78XX_FCT_TX_FIFO_END 0x0CC
33 #define LAN78XX_FCT_FLOW 0x0D0
35 #define LAN78XX_MAF_BASE 0x400
36 #define LAN78XX_MAF_HIX 0x00
37 #define LAN78XX_MAF_LOX 0x04
38 #define LAN78XX_MAF_HI_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_HIX)
39 #define LAN78XX_MAF_LO_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_LOX)
40 #define LAN78XX_MAF_HI(index) (LAN78XX_MAF_BASE + (8 * (index)) + \
42 #define LAN78XX_MAF_LO(index) (LAN78XX_MAF_BASE + (8 * (index)) + \
44 #define LAN78XX_MAF_HI_VALID BIT(31)
47 #define LAN78XX_OTP_BASE_ADDR 0x00001000
49 #define LAN78XX_OTP_PWR_DN (LAN78XX_OTP_BASE_ADDR + 4 * 0x00)
50 #define LAN78XX_OTP_PWR_DN_PWRDN_N BIT(0)
52 #define LAN78XX_OTP_ADDR1 (LAN78XX_OTP_BASE_ADDR + 4 * 0x01)
53 #define LAN78XX_OTP_ADDR1_15_11 0x1F
55 #define LAN78XX_OTP_ADDR2 (LAN78XX_OTP_BASE_ADDR + 4 * 0x02)
56 #define LAN78XX_OTP_ADDR2_10_3 0xFF
58 #define LAN78XX_OTP_RD_DATA (LAN78XX_OTP_BASE_ADDR + 4 * 0x06)
60 #define LAN78XX_OTP_FUNC_CMD (LAN78XX_OTP_BASE_ADDR + 4 * 0x08)
61 #define LAN78XX_OTP_FUNC_CMD_READ BIT(0)
63 #define LAN78XX_OTP_CMD_GO (LAN78XX_OTP_BASE_ADDR + 4 * 0x0A)
64 #define LAN78XX_OTP_CMD_GO_GO BIT(0)
66 #define LAN78XX_OTP_STATUS (LAN78XX_OTP_BASE_ADDR + 4 * 0x0C)
67 #define LAN78XX_OTP_STATUS_BUSY BIT(0)
69 #define LAN78XX_OTP_INDICATOR_1 0xF3
70 #define LAN78XX_OTP_INDICATOR_2 0xF7
73 * Lan78xx infrastructure commands
75 static int lan78xx_read_raw_otp(struct usb_device *udev, u32 offset,
82 ret = lan7x_read_reg(udev, LAN78XX_OTP_PWR_DN, &buf);
86 if (buf & LAN78XX_OTP_PWR_DN_PWRDN_N) {
87 /* clear it and wait to be cleared */
88 ret = lan7x_write_reg(udev, LAN78XX_OTP_PWR_DN, 0);
92 ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_PWR_DN_PWRDN_N",
94 LAN78XX_OTP_PWR_DN_PWRDN_N,
100 for (i = 0; i < length; i++) {
101 ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR1,
102 ((offset + i) >> 8) &
103 LAN78XX_OTP_ADDR1_15_11);
106 ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR2,
107 ((offset + i) & LAN78XX_OTP_ADDR2_10_3));
111 ret = lan7x_write_reg(udev, LAN78XX_OTP_FUNC_CMD,
112 LAN78XX_OTP_FUNC_CMD_READ);
115 ret = lan7x_write_reg(udev, LAN78XX_OTP_CMD_GO,
116 LAN78XX_OTP_CMD_GO_GO);
121 ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_STATUS_BUSY",
123 LAN78XX_OTP_STATUS_BUSY,
128 ret = lan7x_read_reg(udev, LAN78XX_OTP_RD_DATA, &buf);
132 data[i] = (u8)(buf & 0xFF);
138 static int lan78xx_read_otp(struct usb_device *udev, u32 offset,
139 u32 length, u8 *data)
144 ret = lan78xx_read_raw_otp(udev, 0, 1, &sig);
147 if (sig == LAN78XX_OTP_INDICATOR_1)
149 else if (sig == LAN78XX_OTP_INDICATOR_2)
153 ret = lan78xx_read_raw_otp(udev, offset, length, data);
157 debug("LAN78x: MAC address from OTP = %pM\n", data);
162 static int lan78xx_read_otp_mac(unsigned char *enetaddr,
163 struct usb_device *udev)
167 memset(enetaddr, 0, 6);
169 ret = lan78xx_read_otp(udev,
173 if (!ret && is_valid_ethaddr(enetaddr)) {
174 /* eeprom values are valid so use them */
175 debug("MAC address read from OTP %pM\n", enetaddr);
178 debug("MAC address read from OTP invalid %pM\n", enetaddr);
180 memset(enetaddr, 0, 6);
184 static int lan78xx_update_flowcontrol(struct usb_device *udev,
185 struct ueth_data *dev)
187 uint32_t flow = 0, fct_flow = 0;
190 ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow);
194 ret = lan7x_write_reg(udev, LAN78XX_FCT_FLOW, fct_flow);
197 return lan7x_write_reg(udev, FLOW, flow);
200 static int lan78xx_read_mac(unsigned char *enetaddr,
201 struct usb_device *udev,
202 struct lan7x_private *priv)
206 int saved = 0, done = 0;
209 * Depends on chip, some EEPROM pins are muxed with LED function.
210 * disable & restore LED function to access EEPROM.
212 if ((priv->chipid == ID_REV_CHIP_ID_7800) ||
213 (priv->chipid == ID_REV_CHIP_ID_7850)) {
214 ret = lan7x_read_reg(udev, HW_CFG, &val);
218 val &= ~(LAN78XX_HW_CFG_LED1_EN | LAN78XX_HW_CFG_LED0_EN);
219 ret = lan7x_write_reg(udev, HW_CFG, val);
225 * Refer to the doc/README.enetaddr and doc/README.usb for
226 * the U-Boot MAC address policy
228 /* try reading mac address from EEPROM, then from OTP */
229 ret = lan7x_read_eeprom_mac(enetaddr, udev);
234 if ((priv->chipid == ID_REV_CHIP_ID_7800) ||
235 (priv->chipid == ID_REV_CHIP_ID_7850)) {
236 ret = lan7x_write_reg(udev, HW_CFG, saved);
240 /* if the EEPROM mac address is good, then exit */
244 /* try reading mac address from OTP if the device is LAN78xx */
245 return lan78xx_read_otp_mac(enetaddr, udev);
248 static int lan78xx_set_receive_filter(struct usb_device *udev)
250 /* No multicast in u-boot for now */
251 return lan7x_write_reg(udev, LAN78XX_RFE_CTL,
252 RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT);
255 /* starts the TX path */
256 static void lan78xx_start_tx_path(struct usb_device *udev)
258 /* Enable Tx at MAC */
259 lan7x_write_reg(udev, MAC_TX, MAC_TX_TXEN);
261 /* Enable Tx at SCSRs */
262 lan7x_write_reg(udev, LAN78XX_FCT_TX_CTL, FCT_TX_CTL_EN);
265 /* Starts the Receive path */
266 static void lan78xx_start_rx_path(struct usb_device *udev)
268 /* Enable Rx at MAC */
269 lan7x_write_reg(udev, MAC_RX,
270 LAN7X_MAC_RX_MAX_SIZE_DEFAULT |
271 MAC_RX_FCS_STRIP | MAC_RX_RXEN);
273 /* Enable Rx at SCSRs */
274 lan7x_write_reg(udev, LAN78XX_FCT_RX_CTL, FCT_RX_CTL_EN);
277 static int lan78xx_basic_reset(struct usb_device *udev,
278 struct ueth_data *dev,
279 struct lan7x_private *priv)
284 ret = lan7x_basic_reset(udev, dev);
288 /* Keep the chip ID */
289 ret = lan7x_read_reg(udev, ID_REV, &val);
292 debug("LAN78xx ID_REV = 0x%08x\n", val);
294 priv->chipid = (val & ID_REV_CHIP_ID_MASK) >> 16;
296 /* Respond to the IN token with a NAK */
297 ret = lan7x_read_reg(udev, LAN78XX_USB_CFG0, &val);
300 val |= LAN78XX_USB_CFG0_BIR;
301 return lan7x_write_reg(udev, LAN78XX_USB_CFG0, val);
304 int lan78xx_write_hwaddr(struct udevice *dev)
306 struct usb_device *udev = dev_get_parent_priv(dev);
307 struct eth_pdata *pdata = dev_get_platdata(dev);
308 unsigned char *enetaddr = pdata->enetaddr;
309 u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
310 u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]);
313 /* set hardware address */
314 ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo);
318 ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi);
322 ret = lan7x_write_reg(udev, LAN78XX_MAF_LO(0), addr_lo);
326 ret = lan7x_write_reg(udev, LAN78XX_MAF_HI(0),
327 addr_hi | LAN78XX_MAF_HI_VALID);
331 debug("MAC addr %pM written\n", enetaddr);
336 static int lan78xx_eth_start(struct udevice *dev)
338 struct usb_device *udev = dev_get_parent_priv(dev);
339 struct lan7x_private *priv = dev_get_priv(dev);
344 /* Reset and read Mac addr were done in probe() */
345 ret = lan78xx_write_hwaddr(dev);
349 ret = lan7x_write_reg(udev, LAN78XX_BURST_CAP, 0);
353 ret = lan7x_write_reg(udev, LAN78XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
357 ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF);
362 ret = lan7x_write_reg(udev, LAN78XX_FCT_RX_FIFO_END,
363 (MAX_RX_FIFO_SIZE - 512) / 512);
367 ret = lan7x_write_reg(udev, LAN78XX_FCT_TX_FIFO_END,
368 (MAX_TX_FIFO_SIZE - 512) / 512);
373 ret = lan7x_write_reg(udev, FLOW, 0);
377 /* Init Rx. Set Vlan, keep default for VLAN on 78xx */
378 ret = lan78xx_set_receive_filter(udev);
382 /* Init PHY, autonego, and link */
383 ret = lan7x_eth_phylib_connect(dev, &priv->ueth);
386 ret = lan7x_eth_phylib_config_start(dev);
391 * MAC_CR has to be set after PHY init.
392 * MAC will auto detect the PHY speed.
394 ret = lan7x_read_reg(udev, MAC_CR, &write_buf);
397 write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP;
398 ret = lan7x_write_reg(udev, MAC_CR, write_buf);
402 lan78xx_start_tx_path(udev);
403 lan78xx_start_rx_path(udev);
405 return lan78xx_update_flowcontrol(udev, &priv->ueth);
408 int lan78xx_read_rom_hwaddr(struct udevice *dev)
410 struct usb_device *udev = dev_get_parent_priv(dev);
411 struct eth_pdata *pdata = dev_get_platdata(dev);
412 struct lan7x_private *priv = dev_get_priv(dev);
415 ret = lan78xx_read_mac(pdata->enetaddr, udev, priv);
417 memset(pdata->enetaddr, 0, 6);
422 static int lan78xx_eth_probe(struct udevice *dev)
424 struct usb_device *udev = dev_get_parent_priv(dev);
425 struct lan7x_private *priv = dev_get_priv(dev);
426 struct ueth_data *ueth = &priv->ueth;
427 struct eth_pdata *pdata = dev_get_platdata(dev);
430 /* Do a reset in order to get the MAC address from HW */
431 if (lan78xx_basic_reset(udev, ueth, priv))
434 /* Get the MAC address */
436 * We must set the eth->enetaddr from HW because the upper layer
437 * will force to use the environmental var (usbethaddr) or random if
438 * there is no valid MAC address in eth->enetaddr.
440 lan78xx_read_mac(pdata->enetaddr, udev, priv);
441 /* Do not return 0 for not finding MAC addr in HW */
443 ret = usb_ether_register(dev, ueth, RX_URB_SIZE);
447 /* Register phylib */
448 return lan7x_phylib_register(dev);
451 static const struct eth_ops lan78xx_eth_ops = {
452 .start = lan78xx_eth_start,
453 .send = lan7x_eth_send,
454 .recv = lan7x_eth_recv,
455 .free_pkt = lan7x_free_pkt,
456 .stop = lan7x_eth_stop,
457 .write_hwaddr = lan78xx_write_hwaddr,
458 .read_rom_hwaddr = lan78xx_read_rom_hwaddr,
461 U_BOOT_DRIVER(lan78xx_eth) = {
462 .name = "lan78xx_eth",
464 .probe = lan78xx_eth_probe,
465 .remove = lan7x_eth_remove,
466 .ops = &lan78xx_eth_ops,
467 .priv_auto_alloc_size = sizeof(struct lan7x_private),
468 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
471 static const struct usb_device_id lan78xx_eth_id_table[] = {
472 { USB_DEVICE(0x0424, 0x7800) }, /* LAN7800 USB Ethernet */
473 { USB_DEVICE(0x0424, 0x7850) }, /* LAN7850 USB Ethernet */
474 { } /* Terminating entry */
477 U_BOOT_USB_DEVICE(lan78xx_eth, lan78xx_eth_id_table);