2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * T1040 QDS board configuration file
30 #ifdef CONFIG_RAMBOOT_PBL
31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
37 /* High Level Configuration Options */
38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
39 #define CONFIG_MP /* support multiple processors */
41 /* support deep sleep */
42 #define CONFIG_DEEP_SLEEP
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
50 #define CONFIG_PCI_INDIRECT_BRIDGE
51 #define CONFIG_PCIE1 /* PCIE controller 1 */
52 #define CONFIG_PCIE2 /* PCIE controller 2 */
53 #define CONFIG_PCIE3 /* PCIE controller 3 */
54 #define CONFIG_PCIE4 /* PCIE controller 4 */
56 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
59 #define CONFIG_ENV_OVERWRITE
61 #ifndef CONFIG_MTD_NOR_FLASH
63 #define CONFIG_FLASH_CFI_DRIVER
64 #define CONFIG_SYS_FLASH_CFI
65 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
68 #ifdef CONFIG_MTD_NOR_FLASH
69 #if defined(CONFIG_SPIFLASH)
70 #define CONFIG_SYS_EXTRA_ENV_RELOC
71 #define CONFIG_ENV_SPI_BUS 0
72 #define CONFIG_ENV_SPI_CS 0
73 #define CONFIG_ENV_SPI_MAX_HZ 10000000
74 #define CONFIG_ENV_SPI_MODE 0
75 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
76 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
77 #define CONFIG_ENV_SECT_SIZE 0x10000
78 #elif defined(CONFIG_SDCARD)
79 #define CONFIG_SYS_EXTRA_ENV_RELOC
80 #define CONFIG_SYS_MMC_ENV_DEV 0
81 #define CONFIG_ENV_SIZE 0x2000
82 #define CONFIG_ENV_OFFSET (512 * 1658)
83 #elif defined(CONFIG_NAND)
84 #define CONFIG_SYS_EXTRA_ENV_RELOC
85 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
86 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
88 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
89 #define CONFIG_ENV_SIZE 0x2000
90 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
92 #else /* CONFIG_MTD_NOR_FLASH */
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
98 unsigned long get_board_sys_clk(void);
99 unsigned long get_board_ddr_clk(void);
102 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
103 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
106 * These can be toggled for performance analysis, otherwise use default.
108 #define CONFIG_SYS_CACHE_STASHING
109 #define CONFIG_BACKSIDE_L2_CACHE
110 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
111 #define CONFIG_BTB /* toggle branch predition */
112 #define CONFIG_DDR_ECC
113 #ifdef CONFIG_DDR_ECC
114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
115 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
118 #define CONFIG_ENABLE_36BIT_PHYS
120 #define CONFIG_ADDR_MAP
121 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
123 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
124 #define CONFIG_SYS_MEMTEST_END 0x00400000
127 * Config the L3 Cache as L3 SRAM
129 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
131 #define CONFIG_SYS_DCSRBAR 0xf0000000
132 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
135 #define CONFIG_ID_EEPROM
136 #define CONFIG_SYS_I2C_EEPROM_NXID
137 #define CONFIG_SYS_EEPROM_BUS_NUM 0
138 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
140 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
141 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
146 #define CONFIG_VERY_BIG_RAM
147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
151 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
153 #define CONFIG_DDR_SPD
154 #define CONFIG_FSL_DDR_INTERACTIVE
156 #define CONFIG_SYS_SPD_BUS_NUM 0
157 #define SPD_EEPROM_ADDRESS 0x51
159 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
164 #define CONFIG_SYS_FLASH_BASE 0xe0000000
165 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
167 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
168 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
170 CSPR_PORT_SIZE_16 | \
173 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
174 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
175 CSPR_PORT_SIZE_16 | \
178 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
183 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
185 /* NOR Flash Timing Params */
186 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
187 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
188 FTIM0_NOR_TEADC(0x5) | \
189 FTIM0_NOR_TEAHC(0x5))
190 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
191 FTIM1_NOR_TRAD_NOR(0x1A) |\
192 FTIM1_NOR_TSEQRAD_NOR(0x13))
193 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
194 FTIM2_NOR_TCH(0x4) | \
195 FTIM2_NOR_TWPH(0x0E) | \
197 #define CONFIG_SYS_NOR_FTIM3 0x0
199 #define CONFIG_SYS_FLASH_QUIET_TEST
200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
209 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
210 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
211 #define QIXIS_BASE 0xffdf0000
212 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
213 #define QIXIS_LBMAP_SWITCH 0x06
214 #define QIXIS_LBMAP_MASK 0x0f
215 #define QIXIS_LBMAP_SHIFT 0
216 #define QIXIS_LBMAP_DFLTBANK 0x00
217 #define QIXIS_LBMAP_ALTBANK 0x04
218 #define QIXIS_RST_CTL_RESET 0x31
219 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
220 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
221 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
222 #define QIXIS_RST_FORCE_MEM 0x01
224 #define CONFIG_SYS_CSPR3_EXT (0xf)
225 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
229 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
230 #define CONFIG_SYS_CSOR3 0x0
231 /* QIXIS Timing parameters for IFC CS3 */
232 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
233 FTIM0_GPCM_TEADC(0x0e) | \
234 FTIM0_GPCM_TEAHC(0x0e))
235 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
236 FTIM1_GPCM_TRAD(0x3f))
237 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
238 FTIM2_GPCM_TCH(0x8) | \
239 FTIM2_GPCM_TWP(0x1f))
240 #define CONFIG_SYS_CS3_FTIM3 0x0
242 #define CONFIG_NAND_FSL_IFC
243 #define CONFIG_SYS_NAND_BASE 0xff800000
244 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
246 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
247 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
248 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
249 | CSPR_MSEL_NAND /* MSEL = NAND */ \
251 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
253 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
254 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
255 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
256 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
257 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
258 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
259 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
261 #define CONFIG_SYS_NAND_ONFI_DETECTION
263 /* ONFI NAND Flash mode0 Timing Params */
264 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
265 FTIM0_NAND_TWP(0x18) | \
266 FTIM0_NAND_TWCHT(0x07) | \
267 FTIM0_NAND_TWH(0x0a))
268 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
269 FTIM1_NAND_TWBE(0x39) | \
270 FTIM1_NAND_TRR(0x0e) | \
271 FTIM1_NAND_TRP(0x18))
272 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
273 FTIM2_NAND_TREH(0x0a) | \
274 FTIM2_NAND_TWHRE(0x1e))
275 #define CONFIG_SYS_NAND_FTIM3 0x0
277 #define CONFIG_SYS_NAND_DDR_LAW 11
278 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
279 #define CONFIG_SYS_MAX_NAND_DEVICE 1
281 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
283 #if defined(CONFIG_NAND)
284 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
285 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
286 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
287 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
288 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
289 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
290 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
291 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
292 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
293 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
294 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
295 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
296 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
297 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
298 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
299 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
300 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
301 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
302 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
303 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
304 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
305 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
306 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
307 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
309 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
310 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
311 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
312 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
313 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
314 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
315 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
316 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
317 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
318 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
319 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
320 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
321 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
322 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
323 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
324 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
325 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
326 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
327 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
328 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
329 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
330 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
331 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
332 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
335 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
337 #if defined(CONFIG_RAMBOOT_PBL)
338 #define CONFIG_SYS_RAMBOOT
341 #define CONFIG_MISC_INIT_R
343 #define CONFIG_HWCONFIG
345 /* define to use L1 as initial stack */
346 #define CONFIG_L1_INIT_RAM
347 #define CONFIG_SYS_INIT_RAM_LOCK
348 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
351 /* The assembler doesn't like typecast */
352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
353 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
354 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
355 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
357 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
358 GENERATED_GBL_DATA_SIZE)
359 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
361 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
362 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
364 /* Serial Port - controlled on board with jumper J8
368 #define CONFIG_SYS_NS16550_SERIAL
369 #define CONFIG_SYS_NS16550_REG_SIZE 1
370 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
372 #define CONFIG_SYS_BAUDRATE_TABLE \
373 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
375 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
376 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
377 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
378 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
381 #define CONFIG_FSL_DIU_FB
382 #ifdef CONFIG_FSL_DIU_FB
383 #define CONFIG_FSL_DIU_CH7301
384 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
385 #define CONFIG_VIDEO_LOGO
386 #define CONFIG_VIDEO_BMP_LOGO
387 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
389 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
390 * disable empty flash sector detection, which is I/O-intensive.
392 #undef CONFIG_SYS_FLASH_EMPTY_INFO
396 #define CONFIG_SYS_I2C
397 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
398 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
399 #define CONFIG_SYS_FSL_I2C2_SPEED 50000
400 #define CONFIG_SYS_FSL_I2C3_SPEED 50000
401 #define CONFIG_SYS_FSL_I2C4_SPEED 50000
402 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
403 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
404 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
405 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
406 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
407 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
408 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
409 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
411 #define I2C_MUX_PCA_ADDR 0x77
412 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
414 /* I2C bus multiplexer */
415 #define I2C_MUX_CH_DEFAULT 0x8
416 #define I2C_MUX_CH_DIU 0xC
418 /* LDI/DVI Encoder for display */
419 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
420 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
426 #define CONFIG_RTC_DS3231 1
427 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
430 * eSPI - Enhanced SPI
432 #define CONFIG_SF_DEFAULT_SPEED 10000000
433 #define CONFIG_SF_DEFAULT_MODE 0
437 * Memory space is mapped 1-1, but I/O space must start from 0.
441 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
443 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
444 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
445 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
446 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
447 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
448 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
450 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
453 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
455 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
456 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
457 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
458 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
459 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
460 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
461 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
462 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
465 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
467 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
468 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
469 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
470 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
471 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
472 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
473 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
474 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
477 /* controller 4, Base address 203000 */
479 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
480 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
482 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
483 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
484 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
485 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
486 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
489 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
490 #endif /* CONFIG_PCI */
493 #define CONFIG_FSL_SATA_V2
494 #ifdef CONFIG_FSL_SATA_V2
495 #define CONFIG_SYS_SATA_MAX_DEVICE 2
497 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
498 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
500 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
501 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
509 #define CONFIG_HAS_FSL_DR_USB
511 #ifdef CONFIG_HAS_FSL_DR_USB
512 #ifdef CONFIG_USB_EHCI_HCD
513 #define CONFIG_USB_EHCI_FSL
514 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
519 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
520 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
521 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
525 #ifndef CONFIG_NOBQFMAN
526 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
527 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
528 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
529 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
530 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
531 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
532 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
533 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
534 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
535 CONFIG_SYS_BMAN_CENA_SIZE)
536 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
537 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
538 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
539 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
540 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
541 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
542 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
543 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
544 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
545 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
546 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
547 CONFIG_SYS_QMAN_CENA_SIZE)
548 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
549 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
551 #define CONFIG_SYS_DPAA_FMAN
552 #define CONFIG_SYS_DPAA_PME
556 /* Default address of microcode for the Linux Fman driver */
557 #if defined(CONFIG_SPIFLASH)
559 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
560 * env, so we got 0x110000.
562 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
563 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
564 #elif defined(CONFIG_SDCARD)
566 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
567 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
568 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
570 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
571 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
572 #elif defined(CONFIG_NAND)
573 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
574 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
576 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
577 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
578 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
580 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
581 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
582 #endif /* CONFIG_NOBQFMAN */
584 #ifdef CONFIG_SYS_DPAA_FMAN
585 #define CONFIG_FMAN_ENET
586 #define CONFIG_PHYLIB_10G
587 #define CONFIG_PHY_VITESSE
588 #define CONFIG_PHY_REALTEK
589 #define CONFIG_PHY_TERANETICS
590 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
591 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
592 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
593 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
596 #ifdef CONFIG_FMAN_ENET
597 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
598 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
600 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
601 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
602 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
603 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
605 #define CONFIG_MII /* MII PHY management */
606 #define CONFIG_ETHPRIME "FM1@DTSEC1"
609 /* Enable VSC9953 L2 Switch driver */
610 #define CONFIG_VSC9953
611 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
612 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
615 * Dynamic MTD Partition support with mtdparts
617 #ifdef CONFIG_MTD_NOR_FLASH
618 #define CONFIG_MTD_DEVICE
619 #define CONFIG_MTD_PARTITIONS
620 #define CONFIG_FLASH_CFI_MTD
626 #define CONFIG_LOADS_ECHO /* echo on for serial download */
627 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
630 * Miscellaneous configurable options
632 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
635 * For booting Linux, the board info and command line data
636 * have to be in the first 64 MB of memory, since this is
637 * the maximum mapped by the Linux kernel during initialization.
639 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
640 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
642 #ifdef CONFIG_CMD_KGDB
643 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
647 * Environment Configuration
649 #define CONFIG_ROOTPATH "/opt/nfsroot"
650 #define CONFIG_BOOTFILE "uImage"
651 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
653 /* default location for tftp and bootm */
654 #define CONFIG_LOADADDR 1000000
656 #define __USB_PHY_TYPE utmi
658 #define CONFIG_EXTRA_ENV_SETTINGS \
659 "hwconfig=fsl_ddr:bank_intlv=auto;" \
660 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
662 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
663 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
664 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
665 "tftpflash=tftpboot $loadaddr $uboot && " \
666 "protect off $ubootaddr +$filesize && " \
667 "erase $ubootaddr +$filesize && " \
668 "cp.b $loadaddr $ubootaddr $filesize && " \
669 "protect on $ubootaddr +$filesize && " \
670 "cmp.b $loadaddr $ubootaddr $filesize\0" \
671 "consoledev=ttyS0\0" \
672 "ramdiskaddr=2000000\0" \
673 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
674 "fdtaddr=1e00000\0" \
675 "fdtfile=t1040qds/t1040qds.dtb\0" \
678 #define CONFIG_LINUX \
679 "setenv bootargs root=/dev/ram rw " \
680 "console=$consoledev,$baudrate $othbootargs;" \
681 "setenv ramdiskaddr 0x02000000;" \
682 "setenv fdtaddr 0x00c00000;" \
683 "setenv loadaddr 0x1000000;" \
684 "bootm $loadaddr $ramdiskaddr $fdtaddr"
686 #define CONFIG_HDBOOT \
687 "setenv bootargs root=/dev/$bdev rw " \
688 "console=$consoledev,$baudrate $othbootargs;" \
689 "tftp $loadaddr $bootfile;" \
690 "tftp $fdtaddr $fdtfile;" \
691 "bootm $loadaddr - $fdtaddr"
693 #define CONFIG_NFSBOOTCOMMAND \
694 "setenv bootargs root=/dev/nfs rw " \
695 "nfsroot=$serverip:$rootpath " \
696 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
697 "console=$consoledev,$baudrate $othbootargs;" \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr - $fdtaddr"
702 #define CONFIG_RAMBOOTCOMMAND \
703 "setenv bootargs root=/dev/ram rw " \
704 "console=$consoledev,$baudrate $othbootargs;" \
705 "tftp $ramdiskaddr $ramdiskfile;" \
706 "tftp $loadaddr $bootfile;" \
707 "tftp $fdtaddr $fdtfile;" \
708 "bootm $loadaddr $ramdiskaddr $fdtaddr"
710 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
712 #include <asm/fsl_secure_boot.h>
714 #endif /* __CONFIG_H */
projects / u-boot / blob