git.sur5r.net Git - u-boot/blob - include/configs/cm5200.h

   1 /*
   2  * (C) Copyright 2003-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  15 #define CONFIG_CM5200           1       /* ... on CM5200 platform */
  16
  17 #define CONFIG_SYS_TEXT_BASE    0xfc000000
  18
  19 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  20
  21 /*
  22  * Supported commands
  23  */
  24 #define CONFIG_CMD_BSP
  25 #define CONFIG_CMD_DATE
  26 #define CONFIG_CMD_DIAG
  27 #define CONFIG_CMD_JFFS2
  28 #define CONFIG_CMD_REGINFO
  29
  30 /*
  31  * Serial console configuration
  32  */
  33 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  34 #define CONFIG_BAUDRATE         57600   /* ... at 57600 bps */
  35 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  36 #define CONFIG_SILENT_CONSOLE   1       /* needed to silence i2c_init() */
  37
  38 /*
  39  * Ethernet configuration
  40  */
  41 #define CONFIG_MPC5xxx_FEC      1
  42 #define CONFIG_MPC5xxx_FEC_MII100
  43 #define CONFIG_PHY_ADDR         0x00
  44 #define CONFIG_ENV_OVERWRITE    1       /* allow overwriting of ethaddr */
  45 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
  46 #define CONFIG_MISC_INIT_R      1
  47 #define CONFIG_MAC_OFFSET       0x35    /* MAC address offset in I2C EEPROM */
  48
  49 /*
  50  * POST support
  51  */
  52 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
  53 #define MPC5XXX_SRAM_POST_SIZE  (MPC5XXX_SRAM_SIZE - 4)
  54 /* List of I2C addresses to be verified by POST */
  55 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_SLAVE,  \
  56                                          CONFIG_SYS_I2C_IO,     \
  57                                          CONFIG_SYS_I2C_EEPROM}
  58
  59 /* display image timestamps */
  60 #define CONFIG_TIMESTAMP        1
  61
  62 /*
  63  * Autobooting
  64  */
  65 #define CONFIG_PREBOOT  "echo;" \
  66         "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
  67         "echo"
  68 #undef CONFIG_BOOTARGS
  69
  70 /*
  71  * Default environment settings
  72  */
  73 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  74         "netdev=eth0\0"                                                 \
  75         "netmask=255.255.0.0\0"                                         \
  76         "ipaddr=192.168.160.33\0"                                       \
  77         "serverip=192.168.1.1\0"                                        \
  78         "gatewayip=192.168.1.1\0"                                       \
  79         "console=ttyPSC0\0"                                             \
  80         "u-boot_addr=100000\0"                                          \
  81         "kernel_addr=200000\0"                                          \
  82         "kernel_addr_flash=fc0c0000\0"                                  \
  83         "fdt_addr=400000\0"                                             \
  84         "fdt_addr_flash=fc0a0000\0"                                     \
  85         "ramdisk_addr=500000\0"                                         \
  86         "rootpath=/opt/eldk-4.1/ppc_6xx\0"                              \
  87         "u-boot=/tftpboot/cm5200/u-boot.bin\0"                          \
  88         "bootfile_fdt=/tftpboot/cm5200/uImage\0"                        \
  89         "fdt_file=/tftpboot/cm5200/cm5200.dtb\0"                        \
  90         "load=tftp ${u-boot_addr} ${u-boot}\0"                          \
  91         "update=prot off fc000000 +${filesize}; "                       \
  92                 "era fc000000 +${filesize}; "                           \
  93                 "cp.b ${u-boot_addr} fc000000 ${filesize}; "            \
  94                 "prot on fc000000 +${filesize}\0"                       \
  95         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  96                 "nfsroot=${serverip}:${rootpath}\0"                     \
  97         "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"            \
  98         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
  99         "addinit=setenv bootargs ${bootargs} init=/linuxrc\0"           \
 100         "addcons=setenv bootargs ${bootargs} "                          \
 101                 "console=${console},${baudrate}\0"                      \
 102         "addip=setenv bootargs ${bootargs} "                            \
 103                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                \
 104                 "${netmask}:${hostname}:${netdev}:off panic=1\0"        \
 105         "flash_flash=run flashargs addinit addip addcons;"              \
 106                 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"      \
 107         "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "             \
 108                 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "      \
 109                 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0"         \
 110         ""
 111 #define CONFIG_BOOTCOMMAND      "run flash_flash"
 112
 113 /*
 114  * Low level configuration
 115  */
 116
 117 /*
 118  * Clock configuration
 119  */
 120 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* SYS_XTAL_IN = 33MHz */
 121 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1       /* IPB = 133MHz */
 122
 123 /*
 124  * Memory map
 125  */
 126 #define CONFIG_SYS_MBAR         0xF0000000
 127 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 128 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 129
 130 #define CONFIG_SYS_LOWBOOT              1
 131
 132 /* Use ON-Chip SRAM until RAM will be available */
 133 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 134 #ifdef CONFIG_POST
 135 /* preserve space for the post_word at end of on-chip SRAM */
 136 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 137 #else
 138 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 139 #endif
 140
 141 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 142 #define CONFIG_BOARD_TYPES      1       /* we use board_type */
 143
 144 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 145
 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 147 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* 384 kB for Monitor */
 148 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* 256 kB for malloc() */
 149 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* initial mem map for Linux */
 150
 151 /*
 152  * Flash configuration
 153  */
 154 #define CONFIG_SYS_FLASH_CFI            1
 155 #define CONFIG_FLASH_CFI_DRIVER 1
 156 #define CONFIG_SYS_FLASH_BASE           0xfc000000
 157 /* we need these despite using CFI */
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks */
 159 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sectors on one chip */
 160 #define CONFIG_SYS_FLASH_SIZE           0x02000000 /* 32 MiB */
 161
 162 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 163 #define CONFIG_SYS_RAMBOOT              1
 164 #undef CONFIG_SYS_LOWBOOT
 165 #endif
 166
 167 /*
 168  * Chip selects configuration
 169  */
 170 /* Boot Chipselect */
 171 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 172 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 173 #define CONFIG_SYS_BOOTCS_CFG           0x00087D31      /* for pci_clk = 33 MHz */
 174 /* use board_early_init_r to enable flash write in CS_BOOT */
 175 #define CONFIG_BOARD_EARLY_INIT_R
 176
 177 /* Flash memory addressing */
 178 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 179 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 180
 181 /* No burst, dead cycle = 1 for CS0 (Flash) */
 182 #define CONFIG_SYS_CS_BURST             0x00000000
 183 #define CONFIG_SYS_CS_DEADCYCLE 0x00000001
 184
 185 /*
 186  * SDRAM configuration
 187  * settings for k4s561632E-xx75, assuming XLB = 132 MHz
 188  */
 189 #define SDRAM_MODE      0x00CD0000      /* CASL 3, burst length 8 */
 190 #define SDRAM_CONTROL   0x514F0000
 191 #define SDRAM_CONFIG1   0xE2333900
 192 #define SDRAM_CONFIG2   0x8EE70000
 193
 194 /*
 195  * MTD configuration
 196  */
 197 #define CONFIG_CMD_MTDPARTS     1
 198 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 199 #define CONFIG_FLASH_CFI_MTD
 200 #define MTDIDS_DEFAULT          "nor0=cm5200-0"
 201 #define MTDPARTS_DEFAULT        "mtdparts=cm5200-0:"                    \
 202                                         "384k(uboot),128k(env),"        \
 203                                         "128k(redund_env),128k(dtb),"   \
 204                                         "2m(kernel),27904k(rootfs),"    \
 205                                         "-(config)"
 206
 207 /*
 208  * I2C configuration
 209  */
 210 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 211 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 212 #define CONFIG_SYS_I2C_SPEED            40000   /* 40 kHz */
 213 #define CONFIG_SYS_I2C_SLAVE            0x0
 214 #define CONFIG_SYS_I2C_IO               0x38    /* PCA9554AD I2C I/O port address */
 215 #define CONFIG_SYS_I2C_EEPROM           0x53    /* I2C EEPROM device address */
 216
 217 /*
 218  * RTC configuration
 219  */
 220 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 221
 222 /*
 223  * USB configuration
 224  */
 225 #define CONFIG_USB_OHCI         1
 226 #define CONFIG_USB_CLOCK        0x0001BBBB
 227 #define CONFIG_USB_CONFIG       0x00001000
 228 /* Partitions (for USB) */
 229 #define CONFIG_MAC_PARTITION    1
 230 #define CONFIG_DOS_PARTITION    1
 231 #define CONFIG_ISO_PARTITION    1
 232
 233 /*
 234  * Invoke our last_stage_init function - needed by fwupdate
 235  */
 236 #define CONFIG_LAST_STAGE_INIT  1
 237
 238 /*
 239  * Environment settings
 240  */
 241 #define CONFIG_ENV_IS_IN_FLASH  1
 242 #define CONFIG_ENV_SIZE         0x10000
 243 #define CONFIG_ENV_SECT_SIZE    0x20000
 244 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 245 /* Configuration of redundant environment */
 246 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 247 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 248
 249 /*
 250  * Pin multiplexing configuration
 251  */
 252
 253 /*
 254  * CS1/GPIO_WKUP_6: GPIO (default)
 255  * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
 256  * IRDA/PSC6: UART
 257  * Ether: Ethernet 100Mbit with MD
 258  * PCI_DIS: PCI controller disabled
 259  * USB: USB
 260  * PSC3: SPI with UART3
 261  * PSC2: UART
 262  * PSC1: UART
 263  */
 264 #define CONFIG_SYS_GPS_PORT_CONFIG      0x10559C44
 265
 266 /*
 267  * Miscellaneous configurable options
 268  */
 269 #define CONFIG_SYS_LONGHELP             1       /* undef to save memory */
 270 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 272 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 273 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 274
 275 #define CONFIG_SYS_ALT_MEMTEST          1
 276 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 277 #define CONFIG_SYS_MEMTEST_END          0x03f00000      /* 1 .. 63 MiB in SDRAM */
 278
 279 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 280
 281 /*
 282  * Various low-level settings
 283  */
 284 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 285 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 286
 287 #define CONFIG_SYS_XLB_PIPELINING       1       /* enable transaction pipeling */
 288
 289 /*
 290  * Cache Configuration
 291  */
 292 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 293 #ifdef CONFIG_CMD_KGDB
 294 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 295 #endif
 296
 297 /*
 298  * Flat Device Tree support
 299  */
 300 #define OF_CPU                  "PowerPC,5200@0"
 301 #define OF_SOC                  "soc5200@f0000000"
 302 #define OF_TBCLK                (bd->bi_busfreq / 4)
 303 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 304
 305 #endif /* __CONFIG_H */