git.sur5r.net Git - u-boot/blob - include/configs/colibri_pxa270.h

   1 /*
   2  * Toradex Colibri PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Board Configuration Options
  15  */
  16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  17 /* Avoid overwriting factory configuration block */
  18 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  19
  20 /* We will never enable dcache because we have to setup MMU first */
  21 #define CONFIG_SYS_DCACHE_OFF
  22
  23 /*
  24  * Environment settings
  25  */
  26 #define CONFIG_ENV_OVERWRITE
  27 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  28 #define CONFIG_ARCH_CPU_INIT
  29 #define CONFIG_BOOTCOMMAND                                              \
  30         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  31                 "bootm 0xa0000000; "                                    \
  32         "fi; "                                                          \
  33         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  34                 "bootm 0xa0000000; "                                    \
  35         "fi; "                                                          \
  36         "bootm 0xc0000;"
  37 #define CONFIG_TIMESTAMP
  38 #define CONFIG_CMDLINE_TAG
  39 #define CONFIG_SETUP_MEMORY_TAGS
  40
  41 /*
  42  * Serial Console Configuration
  43  */
  44
  45 /*
  46  * Bootloader Components Configuration
  47  */
  48
  49 /* I2C support */
  50 #ifdef CONFIG_SYS_I2C
  51 #define CONFIG_SYS_I2C_PXA
  52 #define CONFIG_PXA_STD_I2C
  53 #define CONFIG_PXA_PWR_I2C
  54 #define CONFIG_SYS_I2C_SPEED            100000
  55 #endif
  56
  57 /* LCD support */
  58 #ifdef CONFIG_LCD
  59 #define CONFIG_PXA_LCD
  60 #define CONFIG_PXA_VGA
  61 #define CONFIG_LCD_LOGO
  62 #endif
  63
  64 /*
  65  * Networking Configuration
  66  */
  67 #ifdef  CONFIG_CMD_NET
  68
  69 #define CONFIG_DRIVER_DM9000            1
  70 #define CONFIG_DM9000_BASE              0x08000000
  71 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  72 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  73 #define CONFIG_NET_RETRY_COUNT          10
  74
  75 #define CONFIG_BOOTP_BOOTFILESIZE
  76 #endif
  77
  78 #define CONFIG_SYS_DEVICE_NULLDEV       1
  79
  80 /*
  81  * Clock Configuration
  82  */
  83 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  84
  85 /*
  86  * DRAM Map
  87  */
  88 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
  89 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  90 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  91
  92 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  93 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  94
  95 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
  96 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
  97
  98 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
  99 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 100 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 101
 102 /*
 103  * NOR FLASH
 104  */
 105 #ifdef  CONFIG_CMD_FLASH
 106 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 107 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 108 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 109
 110 #define CONFIG_SYS_FLASH_CFI
 111 #define CONFIG_FLASH_CFI_DRIVER         1
 112 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 113
 114 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 116
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 119 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 120 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
 121
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 123 #define CONFIG_SYS_FLASH_PROTECTION             1
 124 #endif
 125
 126 #define CONFIG_SYS_MONITOR_BASE         0x0
 127 #define CONFIG_SYS_MONITOR_LEN          0x40000
 128
 129 /* Skip factory configuration block */
 130 #define CONFIG_ENV_ADDR                 \
 131                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 132 #define CONFIG_ENV_SIZE                 0x40000
 133 #define CONFIG_ENV_SECT_SIZE            0x40000
 134
 135 /*
 136  * GPIO settings
 137  */
 138 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 139 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 140 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 141 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 142
 143 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 144 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 145 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 146 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 147
 148 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 149 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 150 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 151 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 152
 153 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 154 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 155 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 156 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 157 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 158 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 159 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 160 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 161
 162 #define CONFIG_SYS_PSSR_VAL     0x30
 163
 164 /*
 165  * Clock settings
 166  */
 167 #define CONFIG_SYS_CKEN         0x00500240
 168 #define CONFIG_SYS_CCCR         0x02000290
 169
 170 /*
 171  * Memory settings
 172  */
 173 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 174 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 175 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 176 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 177 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 178 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 179 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 180 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 181
 182 /*
 183  * PCMCIA and CF Interfaces
 184  */
 185 #define CONFIG_SYS_MECR_VAL     0x00000000
 186 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 187 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 188 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 189 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 190 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 191 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 192
 193 #include "pxa-common.h"
 194
 195 #endif /* __CONFIG_H */