git.sur5r.net Git - u-boot/blob - include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * Corenet DS style board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #ifdef CONFIG_SECURE_BOOT
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #ifdef CONFIG_NAND
  19 #define CONFIG_RAMBOOT_NAND
  20 #endif
  21 #define CONFIG_BOOTSCRIPT_COPY_RAM
  22 #else
  23 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  26 #if defined(CONFIG_TARGET_P3041DS)
  27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  28 #elif defined(CONFIG_TARGET_P4080DS)
  29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  30 #elif defined(CONFIG_TARGET_P5020DS)
  31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  32 #elif defined(CONFIG_TARGET_P5040DS)
  33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  34 #endif
  35 #endif
  36 #endif
  37
  38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  39 /* Set 1M boot space */
  40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  42                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  44 #endif
  45
  46 /* High Level Configuration Options */
  47 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  48 #define CONFIG_MP                       /* support multiple processors */
  49
  50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  52 #endif
  53
  54 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  55 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  56 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  57 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  58 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  59 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  60
  61 #define CONFIG_ENV_OVERWRITE
  62
  63 #ifndef CONFIG_MTD_NOR_FLASH
  64 #else
  65 #define CONFIG_FLASH_CFI_DRIVER
  66 #define CONFIG_SYS_FLASH_CFI
  67 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  68 #endif
  69
  70 #if defined(CONFIG_SPIFLASH)
  71 #define CONFIG_SYS_EXTRA_ENV_RELOC
  72 #define CONFIG_ENV_SPI_BUS              0
  73 #define CONFIG_ENV_SPI_CS               0
  74 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  75 #define CONFIG_ENV_SPI_MODE             0
  76 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  77 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  78 #define CONFIG_ENV_SECT_SIZE            0x10000
  79 #elif defined(CONFIG_SDCARD)
  80 #define CONFIG_SYS_EXTRA_ENV_RELOC
  81 #define CONFIG_FSL_FIXED_MMC_LOCATION
  82 #define CONFIG_SYS_MMC_ENV_DEV          0
  83 #define CONFIG_ENV_SIZE                 0x2000
  84 #define CONFIG_ENV_OFFSET               (512 * 1658)
  85 #elif defined(CONFIG_NAND)
  86 #define CONFIG_SYS_EXTRA_ENV_RELOC
  87 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  88 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  89 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  90 #define CONFIG_ENV_ADDR         0xffe20000
  91 #define CONFIG_ENV_SIZE         0x2000
  92 #elif defined(CONFIG_ENV_IS_NOWHERE)
  93 #define CONFIG_ENV_SIZE         0x2000
  94 #else
  95 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  96 #define CONFIG_ENV_SIZE         0x2000
  97 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  98 #endif
  99
 100 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 101
 102 /*
 103  * These can be toggled for performance analysis, otherwise use default.
 104  */
 105 #define CONFIG_SYS_CACHE_STASHING
 106 #define CONFIG_BACKSIDE_L2_CACHE
 107 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 108 #define CONFIG_BTB                      /* toggle branch predition */
 109 #define CONFIG_DDR_ECC
 110 #ifdef CONFIG_DDR_ECC
 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 112 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 113 #endif
 114
 115 #define CONFIG_ENABLE_36BIT_PHYS
 116
 117 #ifdef CONFIG_PHYS_64BIT
 118 #define CONFIG_ADDR_MAP
 119 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 120 #endif
 121
 122 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 123 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 124 #define CONFIG_SYS_MEMTEST_END          0x00400000
 125
 126 /*
 127  *  Config the L3 Cache as L3 SRAM
 128  */
 129 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 130 #ifdef CONFIG_PHYS_64BIT
 131 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 132 #else
 133 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 134 #endif
 135 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 136 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 137
 138 #ifdef CONFIG_PHYS_64BIT
 139 #define CONFIG_SYS_DCSRBAR              0xf0000000
 140 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 141 #endif
 142
 143 /* EEPROM */
 144 #define CONFIG_ID_EEPROM
 145 #define CONFIG_SYS_I2C_EEPROM_NXID
 146 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 148 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 149
 150 /*
 151  * DDR Setup
 152  */
 153 #define CONFIG_VERY_BIG_RAM
 154 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 155 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 156
 157 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 158 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 159
 160 #define CONFIG_DDR_SPD
 161
 162 #define CONFIG_SYS_SPD_BUS_NUM  1
 163 #define SPD_EEPROM_ADDRESS1     0x51
 164 #define SPD_EEPROM_ADDRESS2     0x52
 165 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 166 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 167
 168 /*
 169  * Local Bus Definitions
 170  */
 171
 172 /* Set the local bus clock 1/8 of platform clock */
 173 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 174
 175 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 176 #ifdef CONFIG_PHYS_64BIT
 177 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 178 #else
 179 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 180 #endif
 181
 182 #define CONFIG_SYS_FLASH_BR_PRELIM \
 183                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 184                  | BR_PS_16 | BR_V)
 185 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 186                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 187
 188 #define CONFIG_SYS_BR1_PRELIM \
 189         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 190 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 191
 192 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 193 #ifdef CONFIG_PHYS_64BIT
 194 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 195 #else
 196 #define PIXIS_BASE_PHYS         PIXIS_BASE
 197 #endif
 198
 199 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 200 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 201
 202 #define PIXIS_LBMAP_SWITCH      7
 203 #define PIXIS_LBMAP_MASK        0xf0
 204 #define PIXIS_LBMAP_SHIFT       4
 205 #define PIXIS_LBMAP_ALTBANK     0x40
 206
 207 #define CONFIG_SYS_FLASH_QUIET_TEST
 208 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 209
 210 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 211 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 212 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 213 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 214
 215 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 216
 217 #if defined(CONFIG_RAMBOOT_PBL)
 218 #define CONFIG_SYS_RAMBOOT
 219 #endif
 220
 221 /* Nand Flash */
 222 #ifdef CONFIG_NAND_FSL_ELBC
 223 #define CONFIG_SYS_NAND_BASE            0xffa00000
 224 #ifdef CONFIG_PHYS_64BIT
 225 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 226 #else
 227 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 228 #endif
 229
 230 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 231 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 232 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 233
 234 /* NAND flash config */
 235 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 236                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 237                                | BR_PS_8               /* Port Size = 8 bit */ \
 238                                | BR_MS_FCM             /* MSEL = FCM */ \
 239                                | BR_V)                 /* valid */
 240 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 241                                | OR_FCM_PGS            /* Large Page*/ \
 242                                | OR_FCM_CSCT \
 243                                | OR_FCM_CST \
 244                                | OR_FCM_CHT \
 245                                | OR_FCM_SCY_1 \
 246                                | OR_FCM_TRLX \
 247                                | OR_FCM_EHTR)
 248
 249 #ifdef CONFIG_NAND
 250 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 251 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 252 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 253 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 254 #else
 255 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 256 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 257 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 258 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 259 #endif
 260 #else
 261 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 262 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 263 #endif /* CONFIG_NAND_FSL_ELBC */
 264
 265 #define CONFIG_SYS_FLASH_EMPTY_INFO
 266 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 267 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 268
 269 #define CONFIG_MISC_INIT_R
 270
 271 #define CONFIG_HWCONFIG
 272
 273 /* define to use L1 as initial stack */
 274 #define CONFIG_L1_INIT_RAM
 275 #define CONFIG_SYS_INIT_RAM_LOCK
 276 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 277 #ifdef CONFIG_PHYS_64BIT
 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 280 /* The assembler doesn't like typecast */
 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 282         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 283           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 284 #else
 285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 288 #endif
 289 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 290
 291 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 292 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 293
 294 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 295 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 296
 297 /* Serial Port - controlled on board with jumper J8
 298  * open - index 2
 299  * shorted - index 1
 300  */
 301 #define CONFIG_SYS_NS16550_SERIAL
 302 #define CONFIG_SYS_NS16550_REG_SIZE     1
 303 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 304
 305 #define CONFIG_SYS_BAUDRATE_TABLE       \
 306         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 307
 308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 310 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 311 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 312
 313 /* I2C */
 314 #define CONFIG_SYS_I2C
 315 #define CONFIG_SYS_I2C_FSL
 316 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 317 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 318 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 319 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 320 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 321 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 322
 323 /*
 324  * RapidIO
 325  */
 326 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 327 #ifdef CONFIG_PHYS_64BIT
 328 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 329 #else
 330 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 331 #endif
 332 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 333
 334 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 335 #ifdef CONFIG_PHYS_64BIT
 336 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 337 #else
 338 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 339 #endif
 340 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 341
 342 /*
 343  * for slave u-boot IMAGE instored in master memory space,
 344  * PHYS must be aligned based on the SIZE
 345  */
 346 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 347 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 350 /*
 351  * for slave UCODE and ENV instored in master memory space,
 352  * PHYS must be aligned based on the SIZE
 353  */
 354 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 355 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 357
 358 /* slave core release by master*/
 359 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 360 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 361
 362 /*
 363  * SRIO_PCIE_BOOT - SLAVE
 364  */
 365 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 366 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 367 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 368                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 369 #endif
 370
 371 /*
 372  * eSPI - Enhanced SPI
 373  */
 374 #define CONFIG_SF_DEFAULT_SPEED         10000000
 375 #define CONFIG_SF_DEFAULT_MODE          0
 376
 377 /*
 378  * General PCI
 379  * Memory space is mapped 1-1, but I/O space must start from 0.
 380  */
 381
 382 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 383 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 384 #ifdef CONFIG_PHYS_64BIT
 385 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 386 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 387 #else
 388 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 389 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 390 #endif
 391 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 392 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 393 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 394 #ifdef CONFIG_PHYS_64BIT
 395 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 396 #else
 397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 398 #endif
 399 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 400
 401 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 402 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 403 #ifdef CONFIG_PHYS_64BIT
 404 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 405 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 406 #else
 407 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 408 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 409 #endif
 410 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 411 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 412 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 413 #ifdef CONFIG_PHYS_64BIT
 414 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 415 #else
 416 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 417 #endif
 418 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 419
 420 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 421 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 422 #ifdef CONFIG_PHYS_64BIT
 423 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 424 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 425 #else
 426 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 427 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 428 #endif
 429 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 430 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 431 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 432 #ifdef CONFIG_PHYS_64BIT
 433 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 434 #else
 435 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 436 #endif
 437 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 438
 439 /* controller 4, Base address 203000 */
 440 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 441 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 442 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 443 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 444 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 445 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 446
 447 /* Qman/Bman */
 448 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 449 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 450 #ifdef CONFIG_PHYS_64BIT
 451 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 452 #else
 453 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 454 #endif
 455 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 456 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 457 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 458 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 459 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 460 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 461                                         CONFIG_SYS_BMAN_CENA_SIZE)
 462 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 463 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 464 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 465 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 466 #ifdef CONFIG_PHYS_64BIT
 467 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 468 #else
 469 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 470 #endif
 471 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 472 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 473 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 474 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 475 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 476 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 477                                         CONFIG_SYS_QMAN_CENA_SIZE)
 478 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 479 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 480
 481 #define CONFIG_SYS_DPAA_FMAN
 482 #define CONFIG_SYS_DPAA_PME
 483 /* Default address of microcode for the Linux Fman driver */
 484 #if defined(CONFIG_SPIFLASH)
 485 /*
 486  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 487  * env, so we got 0x110000.
 488  */
 489 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 490 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 491 #elif defined(CONFIG_SDCARD)
 492 /*
 493  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 494  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 495  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 496  */
 497 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 498 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 499 #elif defined(CONFIG_NAND)
 500 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 501 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 502 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 503 /*
 504  * Slave has no ucode locally, it can fetch this from remote. When implementing
 505  * in two corenet boards, slave's ucode could be stored in master's memory
 506  * space, the address can be mapped from slave TLB->slave LAW->
 507  * slave SRIO or PCIE outbound window->master inbound window->
 508  * master LAW->the ucode address in master's memory space.
 509  */
 510 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 511 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 512 #else
 513 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 514 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 515 #endif
 516 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 517 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 518
 519 #ifdef CONFIG_SYS_DPAA_FMAN
 520 #define CONFIG_FMAN_ENET
 521 #define CONFIG_PHYLIB_10G
 522 #define CONFIG_PHY_VITESSE
 523 #define CONFIG_PHY_TERANETICS
 524 #endif
 525
 526 #ifdef CONFIG_PCI
 527 #define CONFIG_PCI_INDIRECT_BRIDGE
 528
 529 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 530 #endif  /* CONFIG_PCI */
 531
 532 /* SATA */
 533 #ifdef CONFIG_FSL_SATA_V2
 534 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 535 #define CONFIG_SATA1
 536 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 537 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 538 #define CONFIG_SATA2
 539 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 540 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 541
 542 #define CONFIG_LBA48
 543 #endif
 544
 545 #ifdef CONFIG_FMAN_ENET
 546 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 547 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 548 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 549 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 550 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 551
 552 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 553 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 554 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 555 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 556 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 557
 558 #define CONFIG_SYS_TBIPA_VALUE  8
 559 #define CONFIG_MII              /* MII PHY management */
 560 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 561 #endif
 562
 563 /*
 564  * Environment
 565  */
 566 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 568
 569 /*
 570 * USB
 571 */
 572 #define CONFIG_HAS_FSL_DR_USB
 573 #define CONFIG_HAS_FSL_MPH_USB
 574
 575 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 576 #define CONFIG_USB_EHCI_FSL
 577 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 578 #endif
 579
 580 #ifdef CONFIG_MMC
 581 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 582 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 583 #endif
 584
 585 /*
 586  * Miscellaneous configurable options
 587  */
 588 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 589
 590 /*
 591  * For booting Linux, the board info and command line data
 592  * have to be in the first 64 MB of memory, since this is
 593  * the maximum mapped by the Linux kernel during initialization.
 594  */
 595 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 596 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 597
 598 #ifdef CONFIG_CMD_KGDB
 599 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 600 #endif
 601
 602 /*
 603  * Environment Configuration
 604  */
 605 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 606 #define CONFIG_BOOTFILE         "uImage"
 607 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 608
 609 /* default location for tftp and bootm */
 610 #define CONFIG_LOADADDR         1000000
 611
 612 #ifdef CONFIG_TARGET_P4080DS
 613 #define __USB_PHY_TYPE  ulpi
 614 #else
 615 #define __USB_PHY_TYPE  utmi
 616 #endif
 617
 618 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 619         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 620         "bank_intlv=cs0_cs1;"                                   \
 621         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 622         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 623         "netdev=eth0\0"                                         \
 624         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 625         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 626         "tftpflash=tftpboot $loadaddr $uboot && "               \
 627         "protect off $ubootaddr +$filesize && "                 \
 628         "erase $ubootaddr +$filesize && "                       \
 629         "cp.b $loadaddr $ubootaddr $filesize && "               \
 630         "protect on $ubootaddr +$filesize && "                  \
 631         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 632         "consoledev=ttyS0\0"                                    \
 633         "ramdiskaddr=2000000\0"                                 \
 634         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 635         "fdtaddr=1e00000\0"                                     \
 636         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 637         "bdev=sda3\0"
 638
 639 #define CONFIG_HDBOOT                                   \
 640         "setenv bootargs root=/dev/$bdev rw "           \
 641         "console=$consoledev,$baudrate $othbootargs;"   \
 642         "tftp $loadaddr $bootfile;"                     \
 643         "tftp $fdtaddr $fdtfile;"                       \
 644         "bootm $loadaddr - $fdtaddr"
 645
 646 #define CONFIG_NFSBOOTCOMMAND                   \
 647         "setenv bootargs root=/dev/nfs rw "     \
 648         "nfsroot=$serverip:$rootpath "          \
 649         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 650         "console=$consoledev,$baudrate $othbootargs;"   \
 651         "tftp $loadaddr $bootfile;"             \
 652         "tftp $fdtaddr $fdtfile;"               \
 653         "bootm $loadaddr - $fdtaddr"
 654
 655 #define CONFIG_RAMBOOTCOMMAND                           \
 656         "setenv bootargs root=/dev/ram rw "             \
 657         "console=$consoledev,$baudrate $othbootargs;"   \
 658         "tftp $ramdiskaddr $ramdiskfile;"               \
 659         "tftp $loadaddr $bootfile;"                     \
 660         "tftp $fdtaddr $fdtfile;"                       \
 661         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 662
 663 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 664
 665 #include <asm/fsl_secure_boot.h>
 666
 667 #endif  /* __CONFIG_H */