git.sur5r.net Git - u-boot/blob - include/configs/km/kmp204x-common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013 Keymile AG
   4  * Valentin Longchamp <valentin.longchamp@keymile.com>
   5  */
   6
   7 #ifndef _CONFIG_KMP204X_H
   8 #define _CONFIG_KMP204X_H
   9
  10 #define CONFIG_KM_DEF_NETDEV    "netdev=eth0\0"
  11
  12 /* an additionnal option is required for UBI as subpage access is
  13  * supported in u-boot */
  14 #define CONFIG_KM_UBI_PART_BOOT_OPTS            ",2048"
  15
  16 #define CONFIG_NAND_ECC_BCH
  17
  18 /* common KM defines */
  19 #include "keymile-common.h"
  20
  21 #define CONFIG_SYS_RAMBOOT
  22 #define CONFIG_RAMBOOT_PBL
  23 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  25 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
  26 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
  27
  28 /* High Level Configuration Options */
  29 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  30 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  31 #define CONFIG_MP                       /* support multiple processors */
  32
  33 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  34 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  35 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  36 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  37 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  38 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  39
  40 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  41
  42 /* Environment in SPI Flash */
  43 #define CONFIG_SYS_EXTRA_ENV_RELOC
  44 #define CONFIG_ENV_SPI_BUS              0
  45 #define CONFIG_ENV_SPI_CS               0
  46 #define CONFIG_ENV_SPI_MAX_HZ           20000000
  47 #define CONFIG_ENV_SPI_MODE             0
  48 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB for u-boot */
  49 #define CONFIG_ENV_SIZE                 0x004000        /* 16K env */
  50 #define CONFIG_ENV_SECT_SIZE            0x010000
  51 #define CONFIG_ENV_OFFSET_REDUND        0x110000
  52 #define CONFIG_ENV_TOTAL_SIZE           0x020000
  53
  54 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  55
  56 #ifndef __ASSEMBLY__
  57 unsigned long get_board_sys_clk(unsigned long dummy);
  58 #endif
  59 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  60
  61 /*
  62  * These can be toggled for performance analysis, otherwise use default.
  63  */
  64 #define CONFIG_SYS_CACHE_STASHING
  65 #define CONFIG_BACKSIDE_L2_CACHE
  66 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  67 #define CONFIG_BTB                      /* toggle branch predition */
  68
  69 #define CONFIG_ENABLE_36BIT_PHYS
  70
  71 #define CONFIG_ADDR_MAP
  72 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  73
  74 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
  75
  76 /*
  77  *  Config the L3 Cache as L3 SRAM
  78  */
  79 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  81                 CONFIG_RAMBOOT_TEXT_BASE)
  82 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  83 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  84
  85 #define CONFIG_SYS_DCSRBAR              0xf0000000
  86 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  87
  88 /*
  89  * DDR Setup
  90  */
  91 #define CONFIG_VERY_BIG_RAM
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  94
  95 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  96 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  97
  98 #define CONFIG_DDR_SPD
  99 #define CONFIG_FSL_DDR_INTERACTIVE
 100
 101 #define CONFIG_SYS_SPD_BUS_NUM  0
 102 #define SPD_EEPROM_ADDRESS      0x54
 103 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 104
 105 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 106 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 107
 108 /******************************************************************************
 109  * (PRAM usage)
 110  * ... -------------------------------------------------------
 111  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 112  * ... |<------------------- pram -------------------------->|
 113  * ... -------------------------------------------------------
 114  * @END_OF_RAM:
 115  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 116  * @CONFIG_KM_PHRAM: address for /var
 117  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 118  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
 119  */
 120
 121 /* size of rootfs in RAM */
 122 #define CONFIG_KM_ROOTFSSIZE    0x0
 123 /* pseudo-non volatile RAM [hex] */
 124 #define CONFIG_KM_PNVRAM        0x80000
 125 /* physical RAM MTD size [hex] */
 126 #define CONFIG_KM_PHRAM         0x100000
 127 /* reserved pram area at the end of memory [hex]
 128  * u-boot reserves some memory for the MP boot page */
 129 #define CONFIG_KM_RESERVED_PRAM 0x1000
 130 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 131  * is not valid yet, which is the case for when u-boot copies itself to RAM */
 132 #define CONFIG_PRAM             ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
 133
 134 #define CONFIG_KM_CRAMFS_ADDR   0x2000000
 135 #define CONFIG_KM_KERNEL_ADDR   0x1000000       /* max kernel size 15.5Mbytes */
 136 #define CONFIG_KM_FDT_ADDR      0x1F80000       /* max dtb    size  0.5Mbytes */
 137
 138 /*
 139  * Local Bus Definitions
 140  */
 141
 142 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
 143 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_8 | LCRR_EADC_2)
 144
 145 /* Nand Flash */
 146 #define CONFIG_NAND_FSL_ELBC
 147 #define CONFIG_SYS_NAND_BASE            0xffa00000
 148 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 149
 150 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 151 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 152 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 153
 154 /* NAND flash config */
 155 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 156                                | BR_PS_8               /* Port Size = 8 bit */ \
 157                                | BR_MS_FCM             /* MSEL = FCM */ \
 158                                | BR_V)                 /* valid */
 159
 160 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB       /* length 256K */ \
 161                                | OR_FCM_BCTLD   /* LBCTL not ass */     \
 162                                | OR_FCM_SCY_1   /* 1 clk wait cycle */  \
 163                                | OR_FCM_RST     /* 1 clk read setup */  \
 164                                | OR_FCM_PGS     /* Large page size */   \
 165                                | OR_FCM_CST)    /* 0.25 command setup */
 166
 167 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 168 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 169
 170 /* QRIO FPGA */
 171 #define CONFIG_SYS_QRIO_BASE            0xfb000000
 172 #define CONFIG_SYS_QRIO_BASE_PHYS       0xffb000000ull
 173
 174 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
 175                                 | BR_PS_8       /* Port Size 8 bits */ \
 176                                 | BR_DECC_OFF   /* no error corr */ \
 177                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 178                                 | BR_V)         /* valid */
 179
 180 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB  /* length 64K */ \
 181                                 | OR_GPCM_BCTLD /* no LCTL assert */ \
 182                                 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
 183                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 184                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 185                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 186
 187 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
 188 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
 189
 190 #define CONFIG_MISC_INIT_F
 191 #define CONFIG_MISC_INIT_R
 192
 193 #define CONFIG_HWCONFIG
 194
 195 /* define to use L1 as initial stack */
 196 #define CONFIG_L1_INIT_RAM
 197 #define CONFIG_SYS_INIT_RAM_LOCK
 198 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 200 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 201 /* The assembler doesn't like typecast */
 202 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 203         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 204           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 205 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 206
 207 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 208                                         GENERATED_GBL_DATA_SIZE)
 209 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 210
 211 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 212 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 213 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 214
 215 /* Serial Port - controlled on board with jumper J8
 216  * open - index 2
 217  * shorted - index 1
 218  */
 219 #define CONFIG_SYS_NS16550_SERIAL
 220 #define CONFIG_SYS_NS16550_REG_SIZE     1
 221 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 222
 223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 225 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 226 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 227
 228 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 229
 230 /* I2C */
 231
 232 #define CONFIG_SYS_I2C
 233 #define CONFIG_SYS_I2C_INIT_BOARD
 234 #define CONFIG_SYS_I2C_SPEED            100000 /* deblocking */
 235 #define CONFIG_SYS_NUM_I2C_BUSES        3
 236 #define CONFIG_SYS_I2C_MAX_HOPS         1
 237 #define CONFIG_SYS_I2C_FSL              /* Use FSL I2C driver */
 238 #define CONFIG_I2C_MULTI_BUS
 239 #define CONFIG_I2C_CMD_TREE
 240 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 241 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 242 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 243 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 244                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 245                                         {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
 246                                 }
 247 #ifndef __ASSEMBLY__
 248 void set_sda(int state);
 249 void set_scl(int state);
 250 int get_sda(void);
 251 int get_scl(void);
 252 #endif
 253
 254 #define CONFIG_KM_IVM_BUS               1       /* I2C1 (Mux-Port 1)*/
 255
 256 /*
 257  * eSPI - Enhanced SPI
 258  */
 259 #define CONFIG_SPI_FLASH_BAR    /* 4 byte-addressing */
 260 #define CONFIG_SF_DEFAULT_SPEED         20000000
 261 #define CONFIG_SF_DEFAULT_MODE          0
 262
 263 /*
 264  * General PCI
 265  * Memory space is mapped 1-1, but I/O space must start from 0.
 266  */
 267
 268 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 269 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 270 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 271 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 272 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 273 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 274 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 275 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 276 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 277
 278 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 279 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 280 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 281 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 282 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 283 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8010000
 284 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 285 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8010000ull
 286 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 287
 288 /* Qman/Bman */
 289 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 290 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 291 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 292 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 293 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 294 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 295 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 296 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 297 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 298                                         CONFIG_SYS_BMAN_CENA_SIZE)
 299 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 300 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 301 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 302 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 303 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 304 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 305 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 306 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 307 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 308 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 309 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 310                                         CONFIG_SYS_QMAN_CENA_SIZE)
 311 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 312 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 313
 314 #define CONFIG_SYS_DPAA_FMAN
 315 #define CONFIG_SYS_DPAA_PME
 316 /* Default address of microcode for the Linux Fman driver
 317  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
 318  * ucode is stored after env, so we got 0x120000.
 319  */
 320 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 321 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
 322 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 323 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 324
 325 #define CONFIG_FMAN_ENET
 326 #define CONFIG_PHYLIB_10G
 327
 328 #define CONFIG_PCI_INDIRECT_BRIDGE
 329
 330 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 331
 332 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 333 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x11
 334 #define CONFIG_SYS_TBIPA_VALUE  8
 335 #define CONFIG_ETHPRIME         "FM1@DTSEC5"
 336
 337 /*
 338  * Environment
 339  */
 340 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 341 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 342
 343 /*
 344  * Hardware Watchdog
 345  */
 346 #define CONFIG_WATCHDOG                 /* enable CPU watchdog */
 347 #define CONFIG_WATCHDOG_PRESC 34        /* wdog prescaler 2^(64-34) (~10min) */
 348 #define CONFIG_WATCHDOG_RC WRC_CHIP     /* reset chip on watchdog event */
 349
 350
 351 /*
 352  * additionnal command line configuration.
 353  */
 354
 355 /* we don't need flash support */
 356 #undef CONFIG_FLASH_CFI_MTD
 357 #undef CONFIG_JFFS2_CMDLINE
 358
 359 /*
 360  * For booting Linux, the board info and command line data
 361  * have to be in the first 64 MB of memory, since this is
 362  * the maximum mapped by the Linux kernel during initialization.
 363  */
 364 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 365 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 366
 367 #ifdef CONFIG_CMD_KGDB
 368 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 369 #endif
 370
 371 #define __USB_PHY_TYPE  utmi
 372 #define CONFIG_USB_EHCI_FSL
 373
 374 /*
 375  * Environment Configuration
 376  */
 377 #define CONFIG_ENV_OVERWRITE
 378 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 379 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 380 #endif
 381
 382 /* architecture specific default bootargs */
 383 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 384
 385 /* FIXME: FDT_ADDR is unspecified */
 386 #define CONFIG_KM_DEF_ENV_CPU                                           \
 387         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 388         "cramfsloadfdt="                                                \
 389                 "cramfsload ${fdt_addr_r} "                             \
 390                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 391         "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"              \
 392         "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0"                \
 393         "update="                                                       \
 394                 "sf probe 0;sf erase 0 +${filesize};"                   \
 395                 "sf write ${load_addr_r} 0 ${filesize};\0"              \
 396         "set_fdthigh=true\0"                                            \
 397         "checkfdt=true\0"                                               \
 398         ""
 399
 400 #define CONFIG_HW_ENV_SETTINGS                                          \
 401         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
 402         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 403         "usb_dr_mode=host\0"
 404
 405 #define CONFIG_KM_NEW_ENV                                               \
 406         "newenv=sf probe 0;"                                            \
 407                 "sf erase " __stringify(CONFIG_ENV_OFFSET) " "          \
 408                 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
 409
 410 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
 411 #ifndef CONFIG_KM_DEF_ARCH
 412 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 413 #endif
 414
 415 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 416         CONFIG_KM_DEF_ENV                                               \
 417         CONFIG_KM_DEF_ARCH                                              \
 418         CONFIG_KM_NEW_ENV                                               \
 419         CONFIG_HW_ENV_SETTINGS                                          \
 420         "EEprom_ivm=pca9547:70:9\0"                                     \
 421         ""
 422
 423 #endif /* _CONFIG_KMP204X_H */