git.sur5r.net Git - u-boot/blob - include/net/pfe_eth/pfe/cbus/util_csr.h

   1 /*
   2  * Copyright 2015-2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017 NXP
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _UTIL_CSR_H_
   9 #define _UTIL_CSR_H_
  10
  11 #define UTIL_VERSION                    (UTIL_CSR_BASE_ADDR + 0x000)
  12 #define UTIL_TX_CTRL                    (UTIL_CSR_BASE_ADDR + 0x004)
  13 #define UTIL_INQ_PKTPTR                 (UTIL_CSR_BASE_ADDR + 0x010)
  14
  15 #define UTIL_HDR_SIZE                   (UTIL_CSR_BASE_ADDR + 0x014)
  16
  17 #define UTIL_PE0_QB_DM_ADDR0            (UTIL_CSR_BASE_ADDR + 0x020)
  18 #define UTIL_PE0_QB_DM_ADDR1            (UTIL_CSR_BASE_ADDR + 0x024)
  19 #define UTIL_PE0_RO_DM_ADDR0            (UTIL_CSR_BASE_ADDR + 0x060)
  20 #define UTIL_PE0_RO_DM_ADDR1            (UTIL_CSR_BASE_ADDR + 0x064)
  21
  22 #define UTIL_MEM_ACCESS_ADDR            (UTIL_CSR_BASE_ADDR + 0x100)
  23 #define UTIL_MEM_ACCESS_WDATA           (UTIL_CSR_BASE_ADDR + 0x104)
  24 #define UTIL_MEM_ACCESS_RDATA           (UTIL_CSR_BASE_ADDR + 0x108)
  25
  26 #define UTIL_TM_INQ_ADDR                (UTIL_CSR_BASE_ADDR + 0x114)
  27 #define UTIL_PE_STATUS                  (UTIL_CSR_BASE_ADDR + 0x118)
  28
  29 #define UTIL_PE_SYS_CLK_RATIO           (UTIL_CSR_BASE_ADDR + 0x200)
  30 #define UTIL_AFULL_THRES                (UTIL_CSR_BASE_ADDR + 0x204)
  31 #define UTIL_GAP_BETWEEN_READS          (UTIL_CSR_BASE_ADDR + 0x208)
  32 #define UTIL_MAX_BUF_CNT                (UTIL_CSR_BASE_ADDR + 0x20c)
  33 #define UTIL_TSQ_FIFO_THRES             (UTIL_CSR_BASE_ADDR + 0x210)
  34 #define UTIL_TSQ_MAX_CNT                (UTIL_CSR_BASE_ADDR + 0x214)
  35 #define UTIL_IRAM_DATA_0                (UTIL_CSR_BASE_ADDR + 0x218)
  36 #define UTIL_IRAM_DATA_1                (UTIL_CSR_BASE_ADDR + 0x21c)
  37 #define UTIL_IRAM_DATA_2                (UTIL_CSR_BASE_ADDR + 0x220)
  38 #define UTIL_IRAM_DATA_3                (UTIL_CSR_BASE_ADDR + 0x224)
  39
  40 #define UTIL_BUS_ACCESS_ADDR            (UTIL_CSR_BASE_ADDR + 0x228)
  41 #define UTIL_BUS_ACCESS_WDATA           (UTIL_CSR_BASE_ADDR + 0x22c)
  42 #define UTIL_BUS_ACCESS_RDATA           (UTIL_CSR_BASE_ADDR + 0x230)
  43
  44 #define UTIL_INQ_AFULL_THRES            (UTIL_CSR_BASE_ADDR + 0x234)
  45 #define UTIL_AXI_CTRL                   (UTIL_CSR_BASE_ADDR + 0x240)
  46
  47 #endif /* _UTIL_CSR_H_ */