sunxi: R40: add gigabit ethernet devicetree node

[u-boot] / arch / arm / dts / sun8i-r40.dtsi

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 48ec2e855a2cb4e1fd882b7fb97005874579e631..2cdfb54282ca5b8ff0f7da329f5ef7b664155074 100644 (file)
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -43,6 +43,8 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 / {
        #address-cells = <1>;
@@ -114,6 +116,39 @@
                #size-cells = <1>;
                ranges;
 
+               nmi_intc: interrupt-controller@1c00030 {
+                       compatible = "allwinner,sun7i-a20-sc-nmi";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       reg = <0x01c00030 0x0c>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               mmc0: mmc@1c0f000 {
+                       compatible = "allwinner,sun8i-r40-mmc",
+                                    "allwinner,sun50i-a64-mmc";
+                       reg = <0x01c0f000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+                       clock-names = "ahb", "mmc";
+                       resets = <&ccu RST_BUS_MMC0>;
+                       reset-names = "ahb";
+                       pinctrl-0 = <&mmc0_pins>;
+                       pinctrl-names = "default";
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               ccu: clock@1c20000 {
+                       compatible = "allwinner,sun8i-r40-ccu";
+                       reg = <0x01c20000 0x400>;
+                       clocks = <&osc24M>, <&osc32k>;
+                       clock-names = "hosc", "losc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                pio: pinctrl@1c20800 {
                        compatible = "allwinner,sun8i-r40-pinctrl";
                        reg = <0x01c20800 0x400>;
@@ -126,12 +161,33 @@
                        #interrupt-cells = <3>;
                        #gpio-cells = <3>;
 
+                       gmac_rgmii_pins: gmac-rgmii-pins {
+                               pins = "PA0", "PA1", "PA2", "PA3",
+                                      "PA4", "PA5", "PA6", "PA7",
+                                      "PA8", "PA10", "PA11", "PA12",
+                                      "PA13", "PA15", "PA16";
+                               function = "gmac";
+                               /*
+                                * data lines in RGMII mode use DDR mode
+                                * and need a higher signal drive strength
+                                */
+                               drive-strength = <40>;
+                       };
+
                        i2c0_pins: i2c0_pins {
                                pins = "PB0", "PB1";
                                function = "i2c0";
                                bias-pull-up;
                        };
 
+                       mmc0_pins: mmc0-pins {
+                               pins = "PF0", "PF1", "PF2",
+                                      "PF3", "PF4", "PF5";
+                               function = "mmc0";
+                               drive-strength = <30>;
+                               bias-pull-up;
+                       };
+
                        uart0_pb_pins: uart0_pb_pins {
                                pins = "PB22", "PB23";
                                function = "uart0";
@@ -159,6 +215,27 @@
                        #size-cells = <0>;
                };
 
+               gmac: ethernet@1c50000 {
+                       compatible = "allwinner,sun8i-r40-gmac";
+                       syscon = <&ccu>;
+                       reg = <0x01c50000 0x10000>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       resets = <&ccu RST_BUS_GMAC>;
+                       reset-names = "stmmaceth";
+                       clocks = <&ccu CLK_BUS_GMAC>;
+                       clock-names = "stmmaceth";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+
+                       gmac_mdio: mdio {
+                               compatible = "snps,dwmac-mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
                gic: interrupt-controller@1c81000 {
                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
                        reg = <0x01c81000 0x1000>,