u32 reserved11;
u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */
u32 usb_clk_cfg; /* 0xcc USB clock control */
- u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
+#ifdef CONFIG_MACH_SUN8I_R40
+ u32 cir0_clk_cfg; /* 0xd0 CIR0 clock control (R40 only) */
+#else
+ u32 gmac_clk_cfg; /* 0xd0 GMAC clock control (not for R40) */
+#endif
u32 reserved12[7];
u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
u32 mtc_clk_cfg; /* 0x158 MTC module clock */
u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
+#ifdef CONFIG_MACH_SUN8I_R40
+ u32 gmac_clk_cfg; /* 0x164 GMAC clock control (R40 only) */
+#else
u32 reserved16;
+#endif
u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
u32 reserved17[4];
* These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
* them 0 - 2 like they were called on older SoCs.
*/
+#define AHB_GATE_OFFSET_USB_OHCI3 31
+#define AHB_GATE_OFFSET_USB_OHCI2 30
+#define AHB_GATE_OFFSET_USB_OHCI1 29
#define AHB_GATE_OFFSET_USB_OHCI0 28
-#define AHB_GATE_OFFSET_USB_EHCI2 27
-#define AHB_GATE_OFFSET_USB_EHCI1 26
+#define AHB_GATE_OFFSET_USB_EHCI3 27
+#define AHB_GATE_OFFSET_USB_EHCI2 26
+#define AHB_GATE_OFFSET_USB_EHCI1 25
#define AHB_GATE_OFFSET_USB_EHCI0 24
#elif defined(CONFIG_MACH_SUN50I)
#define AHB_GATE_OFFSET_USB_OHCI0 28
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#endif
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5)
#define AHB_GATE_OFFSET_USB0 23
#elif !defined(CONFIG_MACH_SUN8I_R40)
#define AHB_GATE_OFFSET_USB0 24