arm: socfpga: stratix10: Enable Stratix10 SoC build

[u-boot] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a413ea4d1b4a015293a3a9cd9b70583ecda1c707..91ea742f3b104baa90c688a24d8f45ceb4de0f51 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,15 +1,39 @@
 if ARCH_SOCFPGA
 
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+       default 0xa2
+
 config TARGET_SOCFPGA_ARRIA5
        bool
+       select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_ARRIA10
+       bool
+       select SPL_BOARD_INIT if SPL
+       select ALTERA_SDRAM
 
 config TARGET_SOCFPGA_CYCLONE5
        bool
+       select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+       bool
+       select ALTERA_SDRAM
+
+config TARGET_SOCFPGA_STRATIX10
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SPIN_TABLE
+       select ARMV8_SET_SMPEN
 
 choice
        prompt "Altera SOCFPGA board select"
        optional
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+       bool "Altera SOCFPGA SoCDK (Arria 10)"
+       select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
        bool "Altera SOCFPGA SoCDK (Arria V)"
        select TARGET_SOCFPGA_ARRIA5
@@ -18,14 +42,43 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
        bool "Altera SOCFPGA SoCDK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_DENX_MCVEVK
-       bool "DENX MCVEVK (Cyclone V)"
+config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+       bool "Devboards DBM-SoC1 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_EBV_SOCRATES
+       bool "EBV SoCrates (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_IS1
+       bool "IS1 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       bool "samtec VIN|ING FPGA (Cyclone V)"
+       select BOARD_LATE_INIT
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SR1500
+       bool "SR1500 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+       bool "Intel SOCFPGA SoCDK (Stratix 10)"
+       select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
        bool "Terasic DE0-Nano-Atlas (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+       bool "Terasic DE10-Nano (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE1_SOC
+       bool "Terasic DE1-SoC (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_SOCKIT
        bool "Terasic SoCkit (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -34,16 +87,30 @@ endchoice
 
 config SYS_BOARD
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
-       default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+       default "is1" if TARGET_SOCFPGA_IS1
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+       default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "sr1500" if TARGET_SOCFPGA_SR1500
+       default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
+       default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
-       default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
+       default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+       default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+       default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
@@ -51,9 +118,17 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
-       default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+       default "socfpga_is1" if TARGET_SOCFPGA_IS1
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+       default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+       default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
+       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif