arm: socfpga: stratix10: Enable Stratix10 SoC build

[u-boot] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index b8fc81b20c2fc71baf1f865dc7b6bc8fd948eafb..91ea742f3b104baa90c688a24d8f45ceb4de0f51 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -20,6 +20,12 @@ config TARGET_SOCFPGA_GEN5
        bool
        select ALTERA_SDRAM
 
+config TARGET_SOCFPGA_STRATIX10
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SPIN_TABLE
+       select ARMV8_SET_SMPEN
+
 choice
        prompt "Altera SOCFPGA board select"
        optional
@@ -36,10 +42,6 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
        bool "Altera SOCFPGA SoCDK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_ARIES_MCVEVK
-       bool "Aries MCVEVK (Cyclone V)"
-       select TARGET_SOCFPGA_CYCLONE5
-
 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        bool "Devboards DBM-SoC1 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -61,6 +63,10 @@ config TARGET_SOCFPGA_SR1500
        bool "SR1500 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+       bool "Intel SOCFPGA SoCDK (Stratix 10)"
+       select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
        bool "Terasic DE0-Nano-Atlas (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -88,17 +94,17 @@ config SYS_BOARD
        default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "is1" if TARGET_SOCFPGA_IS1
-       default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
+       default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
        default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
-       default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
+       default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
        default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
        default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -119,10 +125,10 @@ config SYS_CONFIG_NAME
        default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "socfpga_is1" if TARGET_SOCFPGA_IS1
-       default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+       default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
        default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif