MIPS: Split I & D cache line size config

[u-boot] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a79224e525ed34bae477b8cecd709aa9588a5eb2..5c30ae981dfdd871817316637862da326ef38fbc 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -252,21 +252,27 @@ config SYS_DCACHE_SIZE
        help
          The total size of the L1 Dcache, if known at compile time.
 
+config SYS_DCACHE_LINE_SIZE
+       hex
+       default 0
+       help
+         The size of L1 Dcache lines, if known at compile time.
+
 config SYS_ICACHE_SIZE
        int
        default 0
        help
          The total size of the L1 ICache, if known at compile time.
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
        int
        default 0
        help
-         The size of L1 cache lines, if known at compile time.
+         The size of L1 Icache lines, if known at compile time.
 
 config SYS_CACHE_SIZE_AUTO
        def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-               SYS_CACHELINE_SIZE = 0
+               SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
        help
          Select this (or let it be auto-selected by not defining any cache
          sizes) in order to allow U-Boot to automatically detect the sizes