mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
+ /* WP(Watch Pending), SW0/1 should be cleared. */
+ mtc0 zero, CP0_CAUSE
+
/* STATUS register */
#ifdef CONFIG_TB0229
li k0, ST0_CU0
and k0, k1
mtc0 k0, CP0_STATUS
- /* CAUSE register */
- mtc0 zero, CP0_CAUSE
-
/* Init Timer */
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE