dm: mmc: sunxi: Add A10/A20 compatible strings

[u-boot] / drivers / mmc / sunxi_mmc.c

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 588574fab6a9a02ff2dae4b49d1a8f1729e209f6..7fa1ae8b162f61a755e4d783755e6eda57757647 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2007-2011
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Aaron <leafy.myeh@allwinnertech.com>
  *
  * MMC driver for allwinner sunxi platform.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -30,6 +29,7 @@ struct sunxi_mmc_priv {
        uint32_t *mclkreg;
        unsigned fatal_err;
        struct gpio_desc cd_gpio;       /* Change Detect GPIO */
+       int cd_inverted;                /* Inverted Card Detect */
        struct sunxi_mmc *reg;
        struct mmc_config cfg;
 };
@@ -96,6 +96,18 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
        unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+       bool new_mode = false;
+       u32 val = 0;
+
+       if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
+               new_mode = true;
+
+       /*
+        * The MMC clock has an extra /2 post-divider when operating in the new
+        * mode.
+        */
+       if (new_mode)
+               hz = hz * 2;
 
        if (hz <= 24000000) {
                pll = CCM_MMC_CTRL_OSCM24;
@@ -134,27 +146,36 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
                oclk_dly = 0;
                sclk_dly = 5;
 #ifdef CONFIG_MACH_SUN9I
-       } else if (hz <= 50000000) {
+       } else if (hz <= 52000000) {
                oclk_dly = 5;
                sclk_dly = 4;
        } else {
-               /* hz > 50000000 */
+               /* hz > 52000000 */
                oclk_dly = 2;
                sclk_dly = 4;
 #else
-       } else if (hz <= 50000000) {
+       } else if (hz <= 52000000) {
                oclk_dly = 3;
                sclk_dly = 4;
        } else {
-               /* hz > 50000000 */
+               /* hz > 52000000 */
                oclk_dly = 1;
                sclk_dly = 4;
 #endif
        }
 
-       writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
-              CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
-              CCM_MMC_CTRL_M(div), priv->mclkreg);
+       if (new_mode) {
+#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+               val = CCM_MMC_CTRL_MODE_SEL_NEW;
+               setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
+#endif
+       } else {
+               val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
+                       CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
+       }
+
+       writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
+              CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 
        debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
              priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
@@ -166,15 +187,16 @@ static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 {
        unsigned int cmd;
        unsigned timeout_msecs = 2000;
+       unsigned long start = get_timer(0);
 
        cmd = SUNXI_MMC_CMD_START |
              SUNXI_MMC_CMD_UPCLK_ONLY |
              SUNXI_MMC_CMD_WAIT_PRE_OVER;
+
        writel(cmd, &priv->reg->cmd);
        while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
-               if (!timeout_msecs--)
+               if (get_timer(start) > timeout_msecs)
                        return -1;
-               udelay(1000);
        }
 
        /* clock update sets various irq status bits, clear these */
@@ -255,18 +277,21 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
        unsigned i;
        unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
        unsigned byte_cnt = data->blocksize * data->blocks;
-       unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
-       if (timeout_usecs < 2000000)
-               timeout_usecs = 2000000;
+       unsigned timeout_msecs = byte_cnt >> 8;
+       unsigned long  start;
+
+       if (timeout_msecs < 2000)
+               timeout_msecs = 2000;
 
        /* Always read / write data through the CPU */
        setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 
+       start = get_timer(0);
+
        for (i = 0; i < (byte_cnt >> 2); i++) {
                while (readl(&priv->reg->status) & status_bit) {
-                       if (!timeout_usecs--)
+                       if (get_timer(start) > timeout_msecs)
                                return -1;
-                       udelay(1);
                }
 
                if (reading)
@@ -282,16 +307,16 @@ static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
                         uint timeout_msecs, uint done_bit, const char *what)
 {
        unsigned int status;
+       unsigned long start = get_timer(0);
 
        do {
                status = readl(&priv->reg->rint);
-               if (!timeout_msecs-- ||
+               if ((get_timer(start) > timeout_msecs) ||
                    (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
                        debug("%s timeout %x\n", what,
                              status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
                        return -ETIMEDOUT;
                }
-               udelay(1000);
        } while (!(status & done_bit));
 
        return 0;
@@ -383,15 +408,16 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
        }
 
        if (cmd->resp_type & MMC_RSP_BUSY) {
+               unsigned long start = get_timer(0);
                timeout_msecs = 2000;
+
                do {
                        status = readl(&priv->reg->status);
-                       if (!timeout_msecs--) {
+                       if (get_timer(start) > timeout_msecs) {
                                debug("busy timeout\n");
                                error = -ETIMEDOUT;
                                goto out;
                        }
-                       udelay(1000);
                } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
        }
 
@@ -498,7 +524,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
        if (ret)
                return NULL;
 
-       return mmc_create(cfg, mmc_host);
+       return mmc_create(cfg, priv);
 }
 #else
 
@@ -523,9 +549,11 @@ static int sunxi_mmc_getcd(struct udevice *dev)
 {
        struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 
-       if (dm_gpio_is_valid(&priv->cd_gpio))
-               return dm_gpio_get_value(&priv->cd_gpio);
+       if (dm_gpio_is_valid(&priv->cd_gpio)) {
+               int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 
+               return cd_state ^ priv->cd_inverted;
+       }
        return 1;
 }
 
@@ -589,6 +617,9 @@ static int sunxi_mmc_probe(struct udevice *dev)
                sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
        }
 
+       /* Check if card detect is inverted */
+       priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
+
        upriv->mmc = &plat->mmc;
 
        /* Reset controller */
@@ -606,7 +637,9 @@ static int sunxi_mmc_bind(struct udevice *dev)
 }
 
 static const struct udevice_id sunxi_mmc_ids[] = {
+       { .compatible = "allwinner,sun4i-a10-mmc" },
        { .compatible = "allwinner,sun5i-a13-mmc" },
+       { .compatible = "allwinner,sun7i-a20-mmc" },
        { }
 };