+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016
* Author: Amit Singh Tomar, amittomer25@gmail.com
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* Ethernet driver for H3/A64/A83T based SoC's
*
* It is derived from the work done by
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
#define AHB_GATE_OFFSET_EPHY 0
-#if defined(CONFIG_MACH_SUN8I_H3)
-#define SUN8I_GPD8_GMAC 2
-#else
-#define SUN8I_GPD8_GMAC 4
-#endif
+/* IO mux settings */
+#define SUN8I_IOMUX_H3 2
+#define SUN8I_IOMUX 4
/* H3/A64 EMAC Register's offset */
#define EMAC_CTL0 0x00
phys_addr_t sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc reset_gpio;
+#endif
};
+
+struct sun8i_eth_pdata {
+ struct eth_pdata eth_pdata;
+ u32 reset_delays[3];
+};
+
+
static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct emac_eth_dev *priv = bus->priv;
+ struct udevice *dev = bus->priv;
+ struct emac_eth_dev *priv = dev_get_priv(dev);
ulong start;
u32 miiaddr = 0;
int timeout = CONFIG_MDIO_TIMEOUT;
static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
- struct emac_eth_dev *priv = bus->priv;
+ struct udevice *dev = bus->priv;
+ struct emac_eth_dev *priv = dev_get_priv(dev);
ulong start;
u32 miiaddr = 0;
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
int ret;
u32 reg;
- reg = readl(priv->sysctl_reg);
+ reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == H3_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, ®);
return -EINVAL;
}
- writel(reg, priv->sysctl_reg);
+ writel(reg, priv->sysctl_reg + 0x30);
return 0;
}
tx_descs_init(priv);
/* PHY Start Up */
- genphy_parse_link(priv->phydev);
+ phy_startup(priv->phydev);
sun8i_adjust_link(priv, priv->phydev);
static int parse_phy_pins(struct udevice *dev)
{
+ struct emac_eth_dev *priv = dev_get_priv(dev);
int offset;
const char *pin_name;
- int drive, pull, i;
+ int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"pinctrl-0");
}
drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,drive", 4);
- pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
- "allwinner,pull", 0);
+ "drive-strength", ~0);
+ if (drive != ~0) {
+ if (drive <= 10)
+ drive = SUN4I_PINCTRL_10_MA;
+ else if (drive <= 20)
+ drive = SUN4I_PINCTRL_20_MA;
+ else if (drive <= 30)
+ drive = SUN4I_PINCTRL_30_MA;
+ else
+ drive = SUN4I_PINCTRL_40_MA;
+ }
+
+ if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
+ pull = SUN4I_PINCTRL_PULL_UP;
+ else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
+ pull = SUN4I_PINCTRL_PULL_DOWN;
+
for (i = 0; ; i++) {
int pin;
pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
- "allwinner,pins", i, NULL);
+ "pins", i, NULL);
if (!pin_name)
break;
- if (pin_name[0] != 'P')
- continue;
- pin = (pin_name[1] - 'A') << 5;
- if (pin >= 26 << 5)
+
+ pin = sunxi_name_to_gpio(pin_name);
+ if (pin < 0)
continue;
- pin += simple_strtol(&pin_name[2], NULL, 10);
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
- sunxi_gpio_set_drv(pin, drive);
- sunxi_gpio_set_pull(pin, pull);
+ if (priv->variant == H3_EMAC)
+ sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
+ else
+ sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
+
+ if (drive != ~0)
+ sunxi_gpio_set_drv(pin, drive);
+ if (pull != ~0)
+ sunxi_gpio_set_pull(pin, pull);
}
if (!i) {
- printf("WARNING: emac: cannot find allwinner,pins property\n");
+ printf("WARNING: emac: cannot find pins property\n");
return -2;
}
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- if (priv->use_internal_phy) {
- /* Set clock gating for ephy */
- setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
-
- /* Deassert EPHY */
- setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
+ if (priv->variant == H3_EMAC) {
+ /* Only H3/H5 have clock controls for internal EPHY */
+ if (priv->use_internal_phy) {
+ /* Set clock gating for ephy */
+ setbits_le32(&ccm->bus_gate4,
+ BIT(AHB_GATE_OFFSET_EPHY));
+
+ /* Deassert EPHY */
+ setbits_le32(&ccm->ahb_reset2_cfg,
+ BIT(AHB_RESET_OFFSET_EPHY));
+ }
}
/* Set clock gating for emac */
setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
}
-static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv)
+#if defined(CONFIG_DM_GPIO)
+static int sun8i_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return 0;
+
+ /* reset the phy */
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[0]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[2]);
+
+ return 0;
+}
+#endif
+
+static int sun8i_mdio_init(const char *name, struct udevice *priv)
{
struct mii_dev *bus = mdio_alloc();
bus->write = sun8i_mdio_write;
snprintf(bus->name, sizeof(bus->name), name);
bus->priv = (void *)priv;
+#if defined(CONFIG_DM_GPIO)
+ bus->reset = sun8i_mdio_reset;
+#endif
return mdio_register(bus);
}
sun8i_emac_board_setup(priv);
sun8i_emac_set_syscon(priv);
- sun8i_mdio_init(dev->name, priv);
+ sun8i_mdio_init(dev->name, dev);
priv->bus = miiphy_get_dev_by_name(dev->name);
return sun8i_phy_init(priv, dev);
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
+ const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
+#ifdef CONFIG_DM_GPIO
+ int reset_flags = GPIOD_IS_OUT;
+ int ret = 0;
+#endif
- pdata->iobase = dev_get_addr_name(dev, "emac");
- priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
+ pdata->iobase = devfdt_get_addr(dev);
+ if (pdata->iobase == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find MAC base address\n", __func__);
+ return -EINVAL;
+ }
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+ offset, reg);
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find syscon base address\n", __func__);
+ return -EINVAL;
+ }
pdata->phy_interface = -1;
priv->phyaddr = -1;
priv->use_internal_phy = false;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy");
- if (offset > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
- -1);
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
+ if (offset < 0) {
+ debug("%s: Cannot find PHY address\n", __func__);
+ return -EINVAL;
+ }
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
priv->variant = dev_get_driver_data(dev);
if (!priv->variant) {
- printf("%s: Missing variant '%s'\n", __func__,
- (char *)priv->variant);
+ printf("%s: Missing variant\n", __func__);
return -EINVAL;
}
if (priv->variant == H3_EMAC) {
- if (fdt_getprop(gd->fdt_blob, node,
- "allwinner,use-internal-phy", NULL))
+ int parent = fdt_parent_offset(gd->fdt_blob, offset);
+
+ if (parent >= 0 &&
+ !fdt_node_check_compatible(gd->fdt_blob, parent,
+ "allwinner,sun8i-h3-mdio-internal"))
priv->use_internal_phy = true;
}
if (!priv->use_internal_phy)
parse_phy_pins(dev);
+#ifdef CONFIG_DM_GPIO
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &priv->reset_gpio, reset_flags);
+
+ if (ret == 0) {
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
+ "snps,reset-delays-us",
+ sun8i_pdata->reset_delays, 3);
+ } else if (ret == -ENOENT) {
+ ret = 0;
+ }
+#endif
+
return 0;
}
.probe = sun8i_emac_eth_probe,
.ops = &sun8i_emac_eth_ops,
.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
projects / u-boot / blobdiff