spi: cadence_qspi: Fix compilation warning

[u-boot] / drivers / spi / cadence_qspi.c

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 1d50f135c9d553eb0181c5949bcda2349187e411..29db6fa36844b78971a7755e4334a7092268f34f 100644 (file)
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2012
  * Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -10,7 +9,7 @@
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include "cadence_qspi.h"
 
 #define CQSPI_STIG_READ                        0
@@ -170,14 +169,12 @@ static int cadence_spi_probe(struct udevice *bus)
 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 {
        struct cadence_spi_priv *priv = dev_get_priv(bus);
-       unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
-       unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
 
        /* Disable QSPI */
        cadence_qspi_apb_controller_disable(priv->regbase);
 
        /* Set SPI mode */
-       cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+       cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 
        /* Enable QSPI */
        cadence_qspi_apb_controller_enable(priv->regbase);
@@ -210,11 +207,11 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
        } else {
                data_bytes = bitlen / 8;
        }
-       debug("%s: len=%d [bytes]\n", __func__, data_bytes);
+       debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
 
        /* Set Chip select */
        cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
-                                   CONFIG_CQSPI_DECODER);
+                                   plat->is_decoded_cs);
 
        if ((flags & SPI_XFER_END) || (flags == 0)) {
                if (priv->cmd_len == 0) {
@@ -284,20 +281,16 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 {
        struct cadence_spi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
        int subnode;
-       u32 data[4];
-       int ret;
 
-       /* 2 base addresses are needed, lets get them from the DT */
-       ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
-       if (ret) {
-               printf("Error: Can't get base addresses (ret=%d)!\n", ret);
-               return -ENODEV;
-       }
-
-       plat->regbase = (void *)data[0];
-       plat->ahbbase = (void *)data[2];
+       plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
+       plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
+       plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs");
+       plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128);
+       plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4);
+       plat->trigger_address = fdtdec_get_uint(blob, node,
+                                               "cdns,trigger-address", 0);
 
        /* All other paramters are embedded in the child node */
        subnode = fdt_first_subnode(blob, node);
@@ -311,13 +304,12 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
                                       500000);
 
        /* Read other parameters from DT */
-       plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
-       plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
-       plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
-       plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
-       plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
-       plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
-       plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
+       plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256);
+       plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16);
+       plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200);
+       plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255);
+       plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20);
+       plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20);
 
        debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
              __func__, plat->regbase, plat->ahbbase, plat->max_hz,