]> git.sur5r.net Git - u-boot/blobdiff - include/configs/P1010RDB.h
configs: Migrate CONFIG_SYS_TEXT_BASE
[u-boot] / include / configs / P1010RDB.h
index 6a444aea61a55f718d38f36bf6c160757ce7dffe..78198059da5844f3170806387d33503ec32c3288 100644 (file)
@@ -18,7 +18,6 @@
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE           0x11001000
 #define CONFIG_SPL_TEXT_BASE           0xD0001000
 #define CONFIG_SPL_PAD_TO              0x18000
 #define CONFIG_SPL_MAX_SIZE            (96 * 1024)
 #ifdef CONFIG_SPIFLASH
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_TEXT_BASE           0x11000000
 #define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
 #else
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE                   0x11001000
 #define CONFIG_SPL_TEXT_BASE                   0xD0001000
 #define CONFIG_SPL_PAD_TO                      0x18000
 #define CONFIG_SPL_MAX_SIZE                    (96 * 1024)
@@ -67,7 +64,6 @@
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 
-#define CONFIG_SYS_TEXT_BASE           0x00201000
 #define CONFIG_SPL_TEXT_BASE           0xFFFFE000
 #define CONFIG_SPL_MAX_SIZE            8192
 #define CONFIG_SPL_RELOC_TEXT_BASE     0x00100000
 #define CONFIG_SPL_PAD_TO      0x20000
 #define CONFIG_TPL_PAD_TO      0x20000
 #define CONFIG_SPL_TARGET      "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE   0x11001000
 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 #endif
 
 #ifdef CONFIG_NAND_SECBOOT     /* NAND Boot */
 #define CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_TEXT_BASE           0x11000000
 #define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
 #endif
 
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE           0xeff40000
-#endif
-
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif