serial: Add Actions Semi OWL UART support

[u-boot] / include / fdtdec.h

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4153a6a00864fcc26ba48f2876aa22cb758db534..c15b2a04a7aea5a17148a8608a15fce3bd3aacb9 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -1,6 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __fdtdec_h
@@ -14,7 +14,7 @@
  * changes to support FDT are minimized.
  */
 
-#include <libfdt.h>
+#include <linux/libfdt.h>
 #include <pci.h>
 
 /*
@@ -136,7 +136,6 @@ enum fdt_compat_id {
        COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
        COMPAT_SAMSUNG_EXYNOS_DWMMC,    /* Exynos DWMMC controller */
        COMPAT_SAMSUNG_EXYNOS_MMC,      /* Exynos MMC controller */
-       COMPAT_MAXIM_MAX77686_PMIC,     /* MAX77686 PMIC */
        COMPAT_GENERIC_SPI_FLASH,       /* Generic SPI Flash chip */
        COMPAT_MAXIM_98095_CODEC,       /* MAX98095 Codec */
        COMPAT_SAMSUNG_EXYNOS5_I2C,     /* Exynos5 High Speed I2C Controller */
@@ -161,6 +160,7 @@ enum fdt_compat_id {
        COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
        COMPAT_ALTERA_SOCFPGA_FPGA0,            /* SOCFPGA FPGA manager */
        COMPAT_ALTERA_SOCFPGA_NOC,              /* SOCFPGA Arria 10 NOC */
+       COMPAT_ALTERA_SOCFPGA_CLK_INIT,         /* SOCFPGA Arria 10 clk init */
 
        COMPAT_COUNT,
 };